System for the correction of the phase error of two in-phase and quadrature signals, corresponding device and method

Patent metadata

Field	Value
Publication number	US-9479208-B2
Application number	US-201514751470-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Sep 30, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A system for correction of the phase error in in-phase and quadrature signals may include a first signal and a second signal. The system includes a first circuit and a second circuit, each circuit configured for receiving a square-wave input signal and supplying a respective square-wave output signal. The output signal is delayed with respect to the input signal and each circuit is configured in such a way that the propagation delay of a rising edge and the propagation delay of a falling edge between the input signal and the output signal are configurable. The first circuit is configured for receiving the first signal, and the second circuit is configured for receiving the second signal.

First claim

That which is claimed is:

1. A system for correction of phase error in first and second square-wave input signals, the system comprising:
a first circuit configured to receive the first square-wave input signal; and
a second circuit configured to receive the second square-wave input signal, each of said first and second circuits configured to
receive a respective one of the first and second square-wave input signals,
supply a square-wave output signal, the square-wave output signal being delayed with respect to the respective one of the first and second square-wave input signals, and
generate a configurable propagation delay of a rising edge, and a configurable propagation delay of a falling edge between the respective one of the first and second square-wave input signals and the square-wave output signal; and

a control circuit configured to
detect a duty cycle in the square-wave output signal of said second circuit,
jointly set the configurable propagation delay of the rising edge and the configurable propagation delay of the falling edge of said second circuit as a function of the duty cycle,
detect a phase shift between the square-wave output signal of said first circuit and the square-wave output signal of said second circuit, and
set the configurable propagation delay of the rising edge and the configurable propagation delay of the falling edge of said first circuit as a function of the phase shift by at least
correcting a difference between rising edges of the square-wave output signals of said first and second circuits, acting on the square-wave output signal of said first circuit without modifying a difference between falling edges of the square-wave output signals of said first and second circuits, and
correcting a difference between falling edges of the square-wave output signals of said first and second circuits, acting on the square-wave output signal of said first circuit without modifying a difference between rising edges of the square-wave output signals of said first and second circuits.

2. The system according to claim 1 wherein said control circuit is configured to supply a first control signal, a second control signal, and a third control signal; wherein the first, second, and third control signals are fed back to said second circuit and said first circuit; wherein the first control signal corrects the duty cycle of the square-wave output signal of said second circuit; wherein the second control signal monitors and corrects the difference between rising edges of the square-wave output signals of said first and second circuits; and wherein the third control signal monitors and corrects the difference between the falling edges of the square-wave output signals of said first and second circuits.

3. The system according to claim 1 wherein said first circuit and said second circuit each comprises:
a current-controlled limiting amplifier;
a first input stage, and a second input stage configured to receive the respective one of the first and second square-wave input signals;
an output stage comprising a first transistor, and a second transistor coupled between a supply voltage and a reference node; and
first and second current generators, at least one of said first current generator and said second current generator being configured to be selectively coupled to said output stage as a function of the respective one of the first and second square-wave input signals.

4. The system according to claim 3 wherein each of said first and second circuits is configured to:
couple, using at least one current mirror, said first current generator selectively to said second transistor of said output stage; and
couple said second current generator selectively to said first transistor of said output stage, said first current generator and said second current generator each comprising voltage-controlled current generators.

5. The system according to claim 3 wherein said first transistor of said output stage comprises a first conductivity type transistor coupled between the supply voltage, and an output node configured to output the square-wave output signal; and wherein said second transistor of said output stage comprises a second conductivity type transistor coupled between said output node configured to output the square-wave output signal, and the reference node.

6. The system according to claim 3 wherein said first input stage comprises:
a first input transistor of a first conductivity type coupled to said first current generator, said first input transistor configured to be enabled via the respective one of the first and second square-wave input signals, and
a first protection transistor configured to allow a current when said first input transistor is disabled;
said first protection transistor of the first conductivity type coupled to said first current generator, and configured to be enabled via an inverted square-wave input signal.

7. The system according to claim 6 wherein said second input stage comprises:
a second input transistor of the first conductivity type coupled to said second current generator and is configured to be enabled via the inverted square-wave input signal; and
a second protection transistor of the first conductivity type being coupled to said second current generator and configured to
allow a current when said second input transistor is disabled, and
be enabled via the respective one of the first and second square-wave input signals.

8. The system according to claim 3 wherein by setting biasing currents of said first current generator and said second current generator in said first circuit and said second circuit to set the configurable propagation delays of the rising edge and of the falling edge of the respective one of the first and second square-wave input signals, respectively.

9. The system according to claim 3 wherein said second circuit is configured to generate an output signal with a duty cycle being varied based upon on a difference of currents of said first current generator and said second current generator; and wherein a sum of currents of said first current generator and said second current generator are constant.

10. The system according to claim 2 wherein said control circuit comprises:
a phase detector; and
first, second, and third low pass filters coupled to said phase detector and each configured to supply a feedback signal for a respective controlled variable; and
first, second, and third error amplifiers respectively coupled to said first, second, and third low pass filters and configured to
compare each feedback signal with a corresponding reference voltage, and
generate, respectively, the first control signal, the second control signal, and the third control signal to control said first circuit and said second circuit.

11. A receiver system comprising:
a receiver circuit; and
a phase-error correction circuit coupled to said receiver circuit for correction of phase error in in-phase (I) and quadrature (Q) signals, said phase-error correction circuit comprising
a first circuit configured to receive the I signal, and
a second circuit configured to receive the Q signal, each of said first and second circuits configured to
receive a square-wave input signal,
supply a square-wave output signal, the square-wave output signal being delayed with respect to the square-wave input signal, and
generate a configurable propagation delay of a rising edge, and a configurable propagation delay of a falling edge between the square-wave input signal and the square-wave output signal, and a control circuit configured to
detect a duty cycle in the square-wave output signal of said second circuit,
jointly set t

Assignees

• St Microelectronics Srl

Inventors

• Papotto Giuseppe
• Palmisano Giuseppe

Classifications

• H04W56/005

  compensating for timing error by adjustment in the receiver · CPC title

• H04L27/364

  Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels · CPC title

• H04W56/0035 Primary

  detecting errors in frequency or phase · CPC title

• H03F3/24

  of transmitter output stages · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title