Analog compensation circuit and method

Patent metadata

Field	Value
Publication number	US-9479198-B2
Application number	US-201514853528-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Aug 20, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Disclosed herein are an analog compensation circuit and a method for tuning an analog compensator in full-duplex transmission systems. An embodiment analog compensation circuit includes a secondary receiver configured to receive and convert a sampled self-interference signal to a baseband self-interference signal. A tuner is coupled to the secondary receiver and configured to receive a baseband transmit signal and the baseband self-interference signal, and to compute complex gains according to the baseband transmit signal and the baseband self-interference signal. An analog compensator is coupled to the tuner and has multiple branches. The analog compensator is configured to receive the complex gains and use them to adjust respective attenuators and phase shifters of the branches. The analog compensator is further configured to process a sample of a transmit signal using the branches, the transmit signal being up-converted from a new baseband transmit signal.

First claim

What is claimed is:

1. An compensation circuit for a multi-transmitter full-duplex transceiver, comprising:
a tuner configured to:
receive N baseband transmit signal samples from each of N transmit chains associated with a respective one of N transmitters, wherein a total of NxN baseband transmit signal samples are received, wherein N is a natural number; and
compute a plurality of complex gains according to the NxN received baseband transmit signal samples and N baseband self-interference signal samples; and

an analog compensator coupled to the tuner, having a plurality of branches, each of the plurality of branches having a voltage-controlled attenuator and a voltage-controlled phase shifter, and configured to:
adjust at least one of the voltage-controlled attenuators and voltage-controlled phase shifters in accordance with an associated gain from the plurality of complex gains; and
generate a compensation signal by combining processed signals from the plurality of branches.

2. The compensation circuit of claim 1 , further comprising a secondary receiver configured to receive and convert a sampled self-interference signal to the N baseband self-interference signals.

3. The compensation circuit of claim 2 , wherein the analog compensator comprises N branch sets, each of the N branch sets having N branches, each branch of the N branches of the N branch sets having the voltage-controlled attenuator and the voltage-controlled phase shifter.

4. The compensation circuit of claim 3 wherein each branch of the N branches of the N branch sets is modeled by a respective transfer function, U(ƒ), to which a respective complex gain, β, of the plurality of complex gains, is applied.

5. The compensation circuit of claim 4 , wherein the tuner is configured to employ a least square technique to solve a system, formed by the plurality of branches of the analog compensator, for the plurality of complex gains in a frequency domain, wherein the system is of a form uβ=H, wherein u is a discrete representation in the frequency domain of respective transfer functions for the plurality of branches, β is the plurality of complex gains, and H is a transfer function for an equivalent channel between the secondary receiver and a transmitter connected to the compensator.

6. The compensation circuit of claim 5 , wherein the tuner is further configured to use a set of K frequencies to form u and h, and wherein K is a natural number.

7. The compensation circuit of claim 6 , wherein the transmit signal is an orthogonal frequency division multiplexed (OFDM) signal and the set of K frequencies includes subcarrier frequencies of the transmit signal.

8. A compensation circuit for a multi-transmitter full-duplex transceiver, comprising:
a tuner having a processor and a memory connected to the processor, the memory having stored thereon instructions that, when executed cause the processor to:
compute a plurality of complex gains according to a baseband transmit signal and a baseband self-interference signal; and

an analog compensator coupled to the tuner, and the analog compensator comprising:
a power splitter connected to a signal input;
a plurality of branches connected in parallel to the power splitter, each of the plurality of branches having at least a voltage-controlled attenuator in series with a voltage-controlled phase shifter; and
a power combiner connected to each of the plurality of branches and to a signal output;

wherein the analog compensator is configured to generate voltage signals according to the plurality of complex gains and adjust the voltage-controlled attenuator and the voltage-controlled phase shifter of at least one the plurality of branches with the voltage signals.

9. The compensation circuit of claim 8 , further comprising a secondary receiver configured to receive and convert a sampled self-interference signal to the baseband self-interference signal.

10. The compensation circuit of claim 8 , wherein each of the plurality of branches further comprises a fixed time delay element; and
wherein, in each of the plurality of branches, the respective voltage-controlled attenuator, the respective voltage-controlled phase shifter and the respective fixed time delay element are connected in series between the power splitter and the power combiner.

11. The compensation circuit of claim 8 , wherein the tuner is configured to employ a least square technique to solve a system, formed by the plurality of branches of the analog compensator, for the plurality of complex gains in a frequency domain;
wherein the system is of a form uβ=h, wherein u is a discrete representation in the frequency domain of respective transfer functions for the plurality of branches, β is the plurality of complex gains, and h is a discrete representation in the frequency domain of a quotient of the baseband self-interference signal divided by the baseband transmit signal.

12. The compensation circuit of claim 11 , wherein the instructions causing the processor to compute a plurality of complex gains according to a baseband transmit signal and a baseband self-interference signal comprises instructions that, when executed, cause the processor to generate N complex gains using a set of K frequencies to form u and h, and wherein N and K are each a natural number.

13. The compensation circuit of claim 12 , wherein the plurality of branches comprises N branches; and
wherein the analog compensator is configured to adjust the voltage-controlled attenuator and the voltage-controlled phase shifter of each of the N branches according to a respective one of the N complex gains.

14. The compensation circuit of claim 12 , wherein the transmit signal is an orthogonal frequency division multiplexed (OFDM) signal and the set of K frequencies includes subcarrier frequencies of the transmit signal.

15. A method of tuning an analog compensation circuit for a multi-transmitter full-duplex transceiver, comprising:
receiving N baseband transmit signal samples from each of N transmit chains associated with a respective one of N transmitters in the multi-transmitter full-duplex receiver, wherein a total of N×N baseband transmit signal samples are received, and wherein N is a natural number;
computing a plurality of complex gains according to the N×N received baseband transmit signal samples and N baseband self-interference signal samples;
adjusting an analog compensator having a plurality of branches by adjusting one or more of the plurality branches in accordance with at least one associated gain of the plurality of complex gains; and
generate a compensation signal by combining processed signals from the plurality of branches.

16. The method of claim 15 , wherein the adjusting the analog compensator comprises controlling at least one of a voltage-controlled attenuator and a voltage-controlled phase shifter in at least one of the plurality of branches in accordance with the least one associated gain of the plurality of complex gains.

17. The method of claim 15 , further comprising:
transmitting at least one first transmit signal that is up-converted from at least one baseband transmit signal;
receiving N self-interference signals resulting from the transmitting;
sampling the self-interference signal in a time domain, thereby generating a sampled self-interference signal; and
converting the sampled self-interference signal into the N baseband self-interference signals.

18. The method of claim 15 , further comprising processing a second transmit signal using the analog compensator to generate a compensa

Assignees

• Futurewei Technologies Inc
• Huwaei Tech Co Ltd

Inventors

• Moher Michael
• Griffiths James Gary

Classifications

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title

• H04B1/0042 Primary

  Digital filtering (H04B1/0035 takes precedence; digital filters per se H03H17/00) · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04L27/2601

  Multicarrier modulation systems · CPC title

• H04B2001/0416

  having gain or transmission power control · CPC title