Modified delta-sigma modulator for phase coherent frequency synthesis applications

Patent metadata

Field	Value
Publication number	US-9479185-B2
Application number	US-201514968180-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 12, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

First claim

What is claimed is:

1. A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency, the synthesizer comprising:
a phase detector; and
a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages, the DSM and the phase detector each being clocked by a reference clock configured to generate a cyclical reference signal, the DSM configured to:
count a number of the cycles of the reference signal;
cause, at each cycle of the reference signal, each subsequent stage of the stages of the DSM to accumulate a sum of a previous stage of the DSM; and
multiply each sum by a fractional divide word to produce a multiplier output,

thereby causing the DSM to output a sequence of words that have a deterministic relationship with respect to the reference clock.

2. The synthesizer of claim 1 , wherein the DSM is configured to control a divide ratio in an analog or digital fractional-N phase-locked loop such that a phase of the synthesized frequency is deterministic from a given point in time with respect to the reference signal.

3. The synthesizer of claim 1 , wherein the DSM is configured to shape quantization noise from phase truncation in a numerically controlled oscillator (NCO) operatively coupled to the reference clock, thereby maintaining no phase bias.

4. The synthesizer of claim 3 , wherein the DSM is configured to compare a truncated multiplied output of each stage of the DSM with a previous truncated multiplied output of the same stage, and to generate carry-out bits for a delta path of the DSM based on the comparison.

5. The synthesizer of claim 1 , wherein the stages are serially arranged.

6. The synthesizer of claim 1 , wherein the number of cycles of the reference signal is the number of cycles of the reference signal generated by the reference clock since a given reset event.

7. The synthesizer of claim 1 , further comprising a plurality of phase coherent fractional-N phase-locked loop synthesizers.

8. A method of maintaining phase coherence of a synthesized frequency using a phase coherent delta-sigma modulator (DSM), the method comprising:
counting, by a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages, a number of cycles of a reference signal generated by a reference clock operatively coupled to the DSM;
causing, at each cycle of the reference signal, each subsequent stage of a plurality of stages of the DSM to accumulate a sum of a previous stage of the DSM; and
multiplying each sum by a fractional divide word,
thereby causing the DSM to output a sequence of words that have a deterministic relationship with respect to the reference clock.

9. The method of claim 8 , further comprising controlling a divide ratio in an analog or digital fractional-N phase-locked loop such that a phase of the synthesized frequency is deterministic from a given point in time with respect to the reference signal.

10. The method of claim 8 , further comprising shaping quantization noise from phase truncation in a numerically controlled oscillator (NCO) operatively coupled to the reference clock, thereby maintaining no phase bias.

11. The method of claim 10 , comparing a truncated result of each stage of the DSM with a previous truncated multiplied result of the same stage, and generating carry-out bits for a delta path of the DSM based on the comparison.

12. The method of claim 8 , wherein the stages are serially arranged.

13. The method of claim 8 , wherein the number of cycles of the reference signal is the number of cycles of the reference signal generated by the reference clock since a given reset event.

14. A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency, the synthesizer comprising:
a reference clock; and
means operatively coupled to the reference clock and configured to output a sequence of signals that tracks with the reference clock.

15. The synthesizer of claim 14 , wherein the means is configured to control a divide ratio in an analog or digital fractional-N phase-locked loop such that a phase of the synthesized frequency is deterministic from a given point in time with respect to the reference signal.

16. The synthesizer of claim 15 , wherein the means is configured to shape the quantization noise from phase truncation in a numerically controlled oscillator (NCO) operatively coupled to the reference clock, thereby maintaining no phase bias.

17. The synthesizer of claim 16 , wherein the means is configured to compare a truncated result of an accumulator stage of a DSM with a previous truncated multiplied result of the same stage, and generate carry-out bits for a delta path of the DSM based on the comparison.

18. The synthesizer of claim 14 , further comprising a plurality of phase coherent fractional-N phase-locked loop synthesizers.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Cali Joseph D
• Turner Steven E

Classifications

• H03L7/1806 Primary

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H03M7/3033

  the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs · CPC title

• H03L7/1976 Primary

  using a phase accumulator for controlling the counter or frequency divider · CPC title