Apparatus and methods for ultrasound probes

Patent metadata

Field	Value
Publication number	US-9479162-B2
Application number	US-201213687654-A
Country	US
Kind code	B2
Filing date	Nov 28, 2012
Priority date	Nov 28, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal's voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal.

First claim

What is claimed is:

1. A receive switch comprising:
a first terminal;
a second terminal;
a first field effect transistor (FET) including a first drain electrically connected to the first terminal, a first gate electrically connected to a gate node, and a first source electrically connected to a source node;
a second FET including a second drain electrically connected to the second terminal, a second source electrically connected to the source node, and a second gate electrically connected to the gate node;
a first threshold detection and control circuit configured to detect a voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is greater than a first threshold voltage;
a second threshold detection and control circuit configured to detect the voltage of the first terminal and to turn off at least one of the first FET or the second FET when the voltage of the first terminal is less than a second threshold voltage; and
a gate bias circuit configured to turn on the first and second FETs when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.

2. The receive switch of claim 1 , wherein the first FET and the second FET are n-type field effect transistors, and wherein the second threshold detection and control circuit is configured to electrically connect the gate node to the source node when the voltage of the first terminal is less than the second threshold voltage.

3. The receive switch of claim 2 , wherein the gate bias circuit comprises a third FET and a first resistor electrically connected in series between the gate node and a power high supply.

4. The receive switch of claim 3 , wherein the third FET includes a third source, the gate bias circuit further comprising a second resistor and a diode electrically connected in series between the power high supply and the third source.

5. The receive switch of claim 2 , wherein the first threshold detection and control circuit comprises a first diode, a third FET, and a resistor electrically connected in series between the first terminal and a first voltage supply.

6. The receive switch of claim 5 , wherein the third FET includes a third source, a third drain, and a third gate, wherein the first diode includes an anode electrically connected to the first terminal and a cathode electrically connected to the third drain, wherein the resistor includes a first end electrically connected to the third source and a second end electrically connected to the first voltage supply, and wherein the third gate is electrically connected to a second voltage supply.

7. The receive switch of claim 6 , further comprising a comparator including an input electrically connected to the first end of the resistor.

8. The receive switch of claim 7 , further comprising a second diode and a fourth FET, wherein the fourth FET includes a fourth source, a fourth drain, and a fourth gate, wherein the second diode includes an anode electrically connected to the gate node and a cathode electrically connected to the fourth drain, and wherein the fourth source is electrically connected to the first voltage supply and the fourth gate is electrically connected to an output of the comparator.

9. The receive switch of claim 7 , further comprising a Zener diode including a cathode electrically connected to the input of the comparator and an anode electrically connected to the first voltage supply.

10. The receive switch of claim 2 , wherein the second threshold detection and control circuit comprises a resistor, a third FET, a fourth FET, and a Zener diode, wherein the third FET includes a third source and a third drain, wherein the fourth FET includes a fourth source, a fourth drain, and a fourth gate, wherein the Zener diode includes an anode electrically connected to the source node and a cathode electrically connected to the third drain and to the fourth gate of the fourth gate, wherein the fourth source is electrically connected to the source node and the fourth drain is electrically connected to the gate node, and wherein the resistor includes a first end electrically connected to the third source and a second end electrically connected to a first voltage supply.

11. The receive switch of claim 1 , further comprising a load balancing circuit, wherein the load balancing circuit is configured to balance a first load current and a second load current, wherein the first load current is associated with a voltage on the first terminal that is greater than the first threshold voltage, and wherein the second load current is associated with a voltage on the first terminal that is less than the second threshold voltage.

12. The receive switch of claim 1 , further comprising a switch disable circuit configured to activate in response to a control signal, wherein the switch disable circuit is configured to turn off at least one of the first FET or the second FET when the switch disable circuit is activated, and wherein the first threshold detection and control circuit is further configured to deactivate the switch disable circuit when the first threshold detection and control circuit determines that the voltage of the first terminal is greater than the first threshold voltage.

13. The receive switch of claim 1 , wherein the first threshold voltage is greater than a ground voltage, and wherein the second threshold voltage is less than the ground voltage.

14. The receive switch of claim 1 , wherein the first FET and the second FET are p-type field effect transistors, wherein the first threshold detection and control circuit is configured to electrically connect the gate node to the source node when the voltage of the first terminal is greater than the first threshold voltage.

15. A method of switching in an ultrasound probe, the method comprising:
receiving an ultrasound signal on an input terminal of a receive switch, the receive switch comprising a first field effect transistor (FET) and a second FET, wherein the first FET includes a first drain electrically connected to the input terminal, a first gate electrically connected to a gate node, and a first source electrically connected to a source node, and wherein the second FET includes a second drain electrically connected to an output terminal, a second source electrically connected to the source node, and a second gate electrically connected to the gate node;
comparing a voltage of the input terminal to a first threshold voltage using a first threshold detection and control circuit, and turning off at least one of the first FET or the second FET using the first threshold detection and control circuit when the voltage of the input terminal of the receive switch is greater than the first threshold voltage;
comparing the voltage of the input terminal to a second threshold voltage using a second threshold detection and control circuit, and turning off at least one of the first FET or the second FET using the second threshold detection and control circuit when the voltage of the input terminal is less than the second threshold voltage; and
turning on the first and second FETs using a gate bias circuit when neither the first threshold detection and control circuit nor the second threshold detection and control circuit is active to turn off the first or second FETs.

16. The method of claim 15 , wherein the first FET and the second FET are n-type field effect transistors, and wherein the second threshold detection and control circuit is configured to electrically connect the

Assignees

• Analog Devices Inc

Inventors

• Barlow Allen R
• Taylor Gerard E
• Petersen Corey D

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• B06B1/0215

  for generating pulses, e.g. bursts of oscillations, envelopes · CPC title