Fabricating electronic device including a semiconductor memory that comprises an inter-layer dielectric layer with first and second nitride layer over stacked structure

Patent metadata

Field	Value
Publication number	US-9478739-B2
Application number	US-201414571235-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Jul 3, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory that comprises:
an inter-layer dielectric layer disposed over a substrate and including a hole therein;
a first nitride layer disposed over sidewalls of the hole;
a selector disposed over the bottom of the hole and over the first nitride layer in the hole;
a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and
a second nitride layer disposed over a top surface and sidewalls of the stacked structure.

2. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:
a contact plug penetrating the inter-layer dielectric layer and contacting the substrate and disposed below the first nitride layer and the selector in the hole.

3. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:
a conductive line disposed over the substrate and being in contact with the selector.

4. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:
a conductive line disposed over the substrate; and
a contact plug for coupling the conductive line to the selector.

5. The electronic device according to claim 1 , wherein the second nitride layer has higher nitrogen density than the first nitride layer.

6. The electronic device according to claim 1 , wherein the selector includes one among selection elements such as a Metal Insulator Transition (MIT) layer, a crested barrier layer and an Ovonic Threshold Switch (OTS) layer.

7. The electronic device according to claim 2 , wherein a line width of the selector is smaller than a line width of a top surface of the contact plug.

8. The electronic device according to claim 1 , wherein the stacked structure further includes:
a first electrode disposed below the variable resistance pattern; and
a second electrode disposed over the variable resistance pattern.

9. The electronic device according to claim 8 , wherein a portion of the first electrode fills a portion of the hole.

10. The electronic device according to claim 8 , wherein the first electrode and the second electrode include a nitride and a transition metal selected from the group consisting of TiN, Pt, W, TaN, Ir, Ni, Cu, Ta, Ti, Hf and Zr.

11. The electronic device according to claim 1 , wherein the variable resistance pattern includes a single-layer structure or a multi-layer structure.

12. The electronic device according to claim 1 , wherein the variable resistance pattern includes one or more of a transition metal oxide, a perovskite-based material, a chalcogenide-based material, a high-K material, and a ferromagnetic material.

13. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory unit is part of the memory unit in the microprocessor.

14. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory unit is part of the cache memory unit in the processor.

15. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory unit is part of the auxiliary memory device or the main memory device in the processing system.

16. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory unit is part of the storage device or the temporary storage device in the data storage system.

17. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory unit is part of the memory or the buffer memory in the memory system.

18. An electronic device comprising a semiconductor memory that comprises:
a selector disposed over a substrate;
a first nitride layer disposed over sidewalls of the selector;
a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and
a second nitride layer disposed over a top surface and sidewalls of the stacked structure.

19. The electronic device according to claim 18 , wherein the semiconductor memory further comprises a contact plug disposed between the substrate and the selector and contacting the selector to connect the selector and the substrate.

20. The electronic device according to claim 18 , wherein the second nitride layer has higher nitrogen density than the first nitride layer.

21. The electronic device according to claim 18 , wherein the selector includes one among selection elements such as a Metal Insulator Transition (MIT) layer, a crested barrier layer and an Ovonic Threshold Switch (OTS) layer.

22. The electronic device according to claim 1

Assignees

• Sk Hynix Inc

Inventors

• Kim Seong-Hyun

Classifications

• H10W20/031

  of conductive parts of the interconnections · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• H01L45/16

  Electricity · mapped topic

• G06F3/0617

  in relation to availability · CPC title

• H01L45/1253 Primary

  Electricity · mapped topic