Diode

Patent metadata

Field	Value
Publication number	US-9478672-B2
Application number	US-201313959904-A
Country	US
Kind code	B2
Filing date	Aug 6, 2013
Priority date	Aug 6, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

First claim

What is claimed is:

1. A diode, comprising:
at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions; and
an insulated substrate which has electric insulation and includes quartz glass, sapphire, or alumina ceramics, wherein
the N-type regions and the P-type regions are formed on the insulated substrate,
the N-type regions and the P-type regions are formed in polycrystalline silicon carbide or single-crystal silicon carbide,
a Zener voltage of a unit diode including a set of the N-type region and the P-type region is between 20 V and, 28 V,
the diode is connected to a secondary side of an ignition coil installed in an internal-combustion engine, and is a constant voltage diode which functions so as to prevent applying a discharge voltage exceeding the Zener voltage to a spark plug, and
the discharge voltage applied to the spark plug is 32 to 38 kV in a range of operating temperature between −30° C. and 120° C.

2. The diode according to claim 1 , wherein
the at least one diode element has a thin-film shape, and
the at least one diode element is laminated on the insulated substrate.

3. The diode according to claim 1 , wherein
the at least one diode element is arranged so as to be meandering,
the at least one diode element being in a state where the P-type regions and the N-type regions are in a line by forming PN junctions in series.

4. The diode according to claim 1 , wherein
the at least one diode element is formed so that the P-type regions and the N-type regions are arranged in a predetermined direction and in a line, and
the at least one diode element comprises a plurality of diode elements which are electrically connected in series by wire bonding, and are arranged so that the P-type regions and the N-type regions are meandering.

5. The diode according to claim 1 , wherein
the at least one diode element is arranged so that the P-type regions and the N-type regions are arranged in a straight line on the insulated substrate.

6. The diode according to claim 1 , wherein the at least one diode element comprises a plurality of diode elements, and the diode further comprising:
a lead frame in which the diode elements are mounted via the insulated substrate;
a positive terminal which is electrically connected to one end of a first diode element of the diode elements; and
a negative terminal which is electrically connected to one end of a second diode element of the diode elements, wherein
the other end of the first diode element and the other end of the second diode element are connected via the lead frame.

7. The diode according to claim 1 , wherein
when a Zener voltage temperature coefficient is expressed as K in an equation: Vz=V0×(1+K×T), where Vz is a Zener voltage of the at least one diode element, T is a temperature of the at least one diode element, and V 0 is the Zener voltage Vz obtained when the temperature is 0° C., the Zener voltage temperature coefficient K is 700 ppm/° C. or less.

Assignees

• Denso Corp

Inventors

• Fukazawa Takeshi

Classifications

• H10P30/22

  using masks · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title