Semiconductor device

US9478648B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9478648-B2
Application numberUS-201514959877-A
CountryUS
Kind codeB2
Filing dateDec 4, 2015
Priority dateJan 19, 2015
Publication dateOct 25, 2016
Grant dateOct 25, 2016

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on one surface of the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively provided in the second semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively provided in the second semiconductor layer so as to be adjacent and connected to the third semiconductor layer; trenches each penetrating the second semiconductor layer to reach the first semiconductor layer, dividing the second semiconductor layer into a base region and a floating region, the base region having the third and fourth semiconductor layers therein, one sidewall of each of the trenches abutting the third semiconductor layer; a fifth semiconductor layer of the second conductivity type provided below and electrically connected to another surface of the first semiconductor layer; an emitter electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer and electrically insulated from the floating region of the second semiconductor layer; a collector electrode electrically connected to the fifth semiconductor layer; a gate electrode provided in each of the trenches; a gate insulating film provided in each of the trenches between the corresponding gate electrode and the trench; a shield electrode provided over the floating region of the second semiconductor layer, the shield electrode being made of a material having an electrical resistivity lower than that of the gate electrode and being electrically connected to the gate electrode; and an insulating film provided between the shield electrode and the floating region of the second semiconductor layer. 2. The semiconductor device according to claim 1 , wherein the shield electrode is made of a conductive film including a single film or a multilayer film comprising one or more of a metal silicide, a metal having a high melting point, and a metallic nitride having a high melting point. 3. The semiconductor device according to claim 2 , wherein a film thickness of the shield electrode is 10 nm to 800 nm. 4. The semiconductor device according to claim 3 , wherein the shield electrode laterally extends above the trench to directly connect to the gate electrode. 5. The semiconductor device according to claim 4 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 6. The semiconductor device according to claim 3 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 7. The semiconductor device according to claim 2 , wherein the shield electrode laterally extends above the trench to directly connect to the gate electrode. 8. The semiconductor device according to claim 7 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 9. The semiconductor device according to claim 2 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 10. The semiconductor device according to claim 1 , wherein a film thickness of the shield electrode is 10 nm to 800 nm. 11. The semiconductor device according to claim 10 , wherein the shield electrode laterally extends above the trench to directly connect to the gate electrode. 12. The semiconductor device according to claim 11 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 13. The semiconductor device according to claim 10 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 14. The semiconductor device according to claim 1 , wherein the shield electrode laterally extends above the trench to directly connect to the gate electrode. 15. The semiconductor device according to claim 14 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film. 16. The semiconductor device according to claim 1 , wherein the insulating film disposed between the shield electrode and the floating region has a thickness greater than that of the gate insulating film.

Assignees

Inventors

Classifications

  • Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673) · CPC title

  • Field plates · CPC title

  • Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

  • Collector regions of BJTs · CPC title

  • Emitter regions of BJTs · CPC title

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Frequently asked questions

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What does patent US9478648B2 cover?
A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode.
Who is the assignee on this patent?
Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D12/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 25 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).