Semiconductor device

Patent metadata

Field	Value
Publication number	US-9478601-B2
Application number	US-201114238474-A
Country	US
Kind code	B2
Filing date	Aug 24, 2011
Priority date	Aug 24, 2011
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

In a semiconductor device, plate-shaped upper electrodes are formed on a lower electrode with a dielectric film interposed therebetween. The lower electrode, the dielectric film, and the upper electrodes constitute MIM capacitors. One of the upper electrodes and another upper electrode that are adjacent to each other are arranged at an equal distance, without the guard ring being interposed therebetween. The upper electrodes positioned on the outermost periphery and the guard ring positioned outside those upper electrodes are arranged at a distance equal to the distance from each other.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a plurality of MIM capacitors arranged in a prescribed region on said main surface of said semiconductor substrate, each MIM capacitor including a lower electrode, a dielectric film, and an upper electrode; and
a guard ring arranged on the main surface of said semiconductor substrate such that, in plan view, the guard ring surrounds said prescribed region,
wherein each MIM capacitor of said plurality of MIM capacitors is arranged at a same predetermined distance from each adjacent MIM capacitor, and
wherein said guard ring is arranged so as to be uniformly spaced by said distance from each MIM capacitor adjacent to said guard ring.

2. The semiconductor device according to claim 1 , wherein
a plan shape of each of said plurality of MIM capacitors is a square.

3. The semiconductor device according to claim 2 , wherein
said MIM capacitors have lengths of 5 mm to 1000 mm per side.

4. The semiconductor device according to claim 2 , wherein
in said plurality of MIM capacitors,
at least two of said MIM capacitors are arranged along a first direction, and
at least two of said MIM capacitors are arranged along a second direction crossing said first direction.

5. The semiconductor device according to claim 2 , wherein
said plurality of MIM capacitors are arranged in equal numbers along a first direction and a second direction crossing the first direction.

6. The semiconductor device according to claim 1 , wherein
a plan shape of each of said plurality of MIM capacitors is a rectangle, and
said plurality of MIM capacitors are arranged along a first direction with shorter sides opposed to each other, and along a second direction with longer sides opposed to each other, and
said plurality of MIM capacitors are arranged so that the number of said MIM capacitors arranged along said first direction is greater than the number of said MIM capacitors arranged along the second direction.

7. The semiconductor device according to claim 1 , wherein
in plan view, said plurality of MIM capacitors are disposed in an annular arrangement, and
a second guard ring is disposed inwardly of said angular arrangement such that a distance between the second guard ring and each MIM capacitor adjacent to said second guard ring equals said predetermined distance.

8. The semiconductor device according to claim 1 , further comprising:
an interlayer insulating film formed on said semiconductor substrate to cover said plurality of MIM capacitors; and
a metal film in contact with a surface of said interlayer insulating film and electrically connected to said upper electrodes of said plurality of MIM capacitors.

9. The semiconductor device according to claim 1 , wherein the guard ring is continuous around the prescribed region.

10. The semiconductor device according to claim 9 , wherein the guard ring completely encloses the prescribed region where the plurality of MIM capacitors are arranged.

Assignees

• Tomita Kazuo
• Yamada Keiichi
• Renesas Electronics Corp

Inventors

• Tomita Kazuo
• Yamada Keiichi

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D84/212

  of only capacitors · CPC title