Semiconductor device

Patent metadata

Field	Value
Publication number	US-9478597-B2
Application number	US-55659309-A
Country	US
Kind code	B2
Filing date	Sep 10, 2009
Priority date	Sep 19, 2008
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate comprising a pixel portion and a common connection portion;
wherein the pixel portion comprises:
a gate electrode over the substrate;
a gate insulating layer over the gate electrode;
a first oxide semiconductor layer over the gate insulating layer;
a channel protective layer over a part of the first oxide semiconductor layer;
a second oxide semiconductor layer and a third oxide semiconductor layer over the first oxide semiconductor layer and the channel protective layer;
a first electrode layer over the gate insulating layer and the second oxide semiconductor layer;
a second electrode layer over the gate insulating layer and the third oxide semiconductor layer;
an insulating layer over the first and second electrode layers and the channel protective layer, the insulating layer comprising a first contact hole formed over the second electrode layer; and
a pixel electrode over the insulating layer and electrically connected to the second electrode layer through the first contact hole,

wherein the common connection portion comprises:
the gate insulating layer over the substrate;
a common potential line over the gate insulating layer;
the insulating layer comprising a second contact hole formed over the common potential line; and
a common electrode layer over the insulating layer and electrically connected to the common potential line through the second contact hole, the common electrode being electrically connectable to a counter electrode,

wherein the first electrode layer, the second electrode layer, and the common potential line are formed of the same material, and
wherein the pixel electrode and the common electrode layer are formed of the same material.

2. The semiconductor device according to claim 1 , wherein the common connection portion further comprises a fourth oxide semiconductor layer interposed between the gate insulating layer and the common potential line, and
wherein the second oxide semiconductor layer, the third oxide semiconductor layer, and the fourth oxide semiconductor layer are formed of the same material.

3. The semiconductor device according to claim 1 , wherein the first to third oxide semiconductor layers include indium, gallium, and zinc.

4. The semiconductor device according to claim 1 , wherein the first electrode layer, the second electrode layer and the common potential line include Ti.

5. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer has a higher oxygen concentration than the second and third oxide semiconductor layers.

6. A semiconductor device comprising:
a substrate comprising a pixel portion and a common connection portion;
wherein the pixel portion comprises:
a gate electrode over the substrate;
a gate insulating layer over the gate electrode;
a first oxide semiconductor layer over the gate insulating layer;
a channel protective layer over a part of the first oxide semiconductor layer;
a second oxide semiconductor layer and a third oxide semiconductor layer over the first oxide semiconductor layer and the channel protective layer;
a first electrode layer over the gate insulating layer and the second oxide semiconductor layer;
a second electrode layer over the gate insulating layer and the third oxide semiconductor layer;
an insulating layer over the first and second electrode layers and the channel protective layer, the insulating layer comprising a first contact hole formed over the second electrode layer; and
a pixel electrode over the insulating layer and electrically connected to the second electrode layer through the first contact hole,

wherein the common connection portion comprises:
an connection electrode layer over the substrate;
the gate insulating layer over the connection electrode layer;
a common potential line over the gate insulating layer;
the insulating layer comprising a second contact hole formed over the common potential line; and
a common electrode layer over the insulating layer and electrically connected to the common potential line through the second contact hole, the common electrode being electrically connectable to a counter electrode,

wherein the first electrode layer, the second electrode layer, and the common potential line are formed of the same material, and
wherein the pixel electrode and the common electrode layer are formed of the same material.

7. The semiconductor device according to claim 6 , wherein the common connection portion further comprises a fourth oxide semiconductor layer interposed between the gate insulating layer and the common potential line, and
wherein the second oxide semiconductor layer, the third oxide semiconductor layer, and the fourth oxide semiconductor layer are formed of the same material.

8. The semiconductor device according to claim 6 , wherein the first to third oxide semiconductor layers include indium, gallium, and zinc.

9. The semiconductor device according to claim 6 , wherein the first electrode layer, the second electrode layer and the common potential line include Ti.

10. The semiconductor device according to claim 6 , wherein the first oxide semiconductor layer has a higher oxygen concentration than the second and third oxide semiconductor layers.

Assignees

• Yamazaki Shunpei
• Akimoto Kengo
• Komori Shigeki
• Uochi Hideki
• Wada Rihito
• Chiba Yoko
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Akimoto Kengo
• Komori Shigeki
• Uochi Hideki
• Wada Rihito
• Chiba Yoko

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10K59/8052

  Cathodes · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title