Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors

Patent metadata

Field	Value
Publication number	US-9478550-B2
Application number	US-201213595854-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Aug 27, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.

First claim

The invention claimed is:

1. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row, the access lines comprising a gate of individual of the transistors, the individual transistors comprising a channel region, a gate dielectric being between the channel region and the gate of the individual transistors;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, the individual conductive lines comprising four straight sides forming a four-major-sided polygon in a vertical cross-section, immediately adjacent of the straight sides joining in a single of four corner regions in the vertical cross-section, one of the four single corner regions being the sole elevationally outermost corner region of the respective individual conductive line in the vertical cross-section, another of the four single corner regions being opposite the one corner region in the vertical cross-section and being the sole elevationally innermost corner region of the respective individual conductive line in the vertical cross-section.

2. The array of claim 1 wherein the individual conductive lines are electrically coupled to one another.

3. The array of claim 1 wherein individual conductive lines are encircled by dielectric material within the array.

4. The array of claim 1 wherein semiconductor material underlies the individual conductive lines, the individual conductive lines have respective bases that are everywhere separated from the underlying semiconductor material by dielectric material.

5. The array of claim 4 wherein the dielectric material comprises a layer of silicon dioxide and a layer of silicon nitride.

6. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, semiconductor material underlying the individual conductive lines, the individual conductive lines having respective bases that are directly against and electrically coupled to the underlying semiconductor material, the semiconductor material underlying the bases having a higher doped region elevationally over a lower doped region, the bases being directly against the higher doped region.

7. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, semiconductor material underlying the individual conductive lines, the individual conductive lines having respective bases that are directly against and electrically coupled to the underlying semiconductor material, the bases being directly against and electrically coupled to the underlying semiconductor material at multiple spaced locations paralleling lengthwise along the individual conductive lines, dielectric material being elevationally between the bases and the underlying semiconductor material longitudinally between the multiple spaced locations along the individual conductive lines.

8. The array of claim 7 wherein the locations are between the vertically-oriented transistors.

9. The array of claim 7 wherein the locations are between each of the vertically-oriented transistors lengthwise along the individual conductive lines.

10. The array of claim 7 wherein the semiconductor material underlying the bases has a higher doped region elevationally over a lower doped region, the bases being directly against the higher doped region at the spaced locations.

11. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, semiconductor material underlying the individual conductive lines, the individual conductive lines having respective bases that are directly against and electrically coupled to the underlying semiconductor material, the bases being directly against and electrically coupled to the underlying semiconductor material continuously lengthwise along the individual conductive lines, the semiconductor material underlying the bases having a higher doped region elevationally over a lower doped region, the bases being directly against the higher doped region continuously lengthwise along the individual conductive lines.

12. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, the individual conductive lines extending vertically inward relative to their immediately adjacent data/sense lines.

13. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, the individual conductive lines having respective tops that are vertically outward relative to their immediately adjacent data/sense lines.

14. An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
individual of the rows comprising an access line interconnecting transistors in that row;
individual of the columns comprising a data/sense line interconnecting transistors in that column; and
a plurality of conductive lines, individual of the conductive lines extending longitudinally parallel and laterally between immediately adjacent of the data/sense lines, the individual conductive lines extending vertically inward and outward relative to their immediately adjacent data/sense lines.

15. An array comprising vertically-oriented transistors, the arra

Assignees

• Karda Kamal M
• Surthi Shyam
• Mueller Wolfgang
• Tang Sanh D
• Micron Technology Inc

Inventors

• Karda Kamal M
• Surthi Shyam
• Mueller Wolfgang
• Tang Sanh D

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H01L21/765

  Electricity · mapped topic

• H01L27/10876 Primary

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic