Semiconductor device, method for manufacturing same, and electronic component

Patent metadata

Field	Value
Publication number	US-9478481-B2
Application number	US-201214345234-A
Country	US
Kind code	B2
Filing date	Nov 14, 2012
Priority date	Nov 15, 2011
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a gate insulating film formed on a surface of the semiconductor substrate;
an interlayer insulating film formed on the gate insulating film;
a surface electrode including a plurality of wiring lines having a damascene structure selectively embedded in the interlayer insulating film with a predetermined pattern and a between-wiring-lines insulating film disposed between the wiring lines adjoining each other, a part of the interlayer insulating film forming the between-wiring-lines insulating film;
a through electrode penetrating the semiconductor substrate and electrically connected to the surface electrode; and
a via insulating film disposed between the through electrode and the semiconductor substrate,
wherein the wiring lines and the between-wiring-lines insulating film are formed to be flush with each other in a connection surface of the wiring lines and the between-wiring-lines insulating film with the through electrode,
wherein the surface electrode further includes
a facing portion facing the through electrode,
a projecting portion projecting in a lateral direction from the facing portion, and
an electrode layer disposed between the gate insulating film and the interlayer insulating film and having a same pattern as one of the wiring lines forming the projecting portion.

2. The semiconductor device according to claim 1 , wherein the wiring lines and the between-wiring-lines insulating film are alternately arranged in a stripe manner in the surface electrode.

3. The semiconductor device according to claim 1 , wherein the wiring lines includes a Cu wiring line.

4. The semiconductor device according to claim 1 , wherein
the interlayer insulating film includes interlayer insulating films,
the surface electrode includes multi-layer electrodes between which the interlayer insulating films are interposed and are stacked together.

5. The semiconductor device according to claim 1 , wherein the semiconductor device includes a surface bump for external connection disposed at a position directly on the through electrode so that the surface electrode is placed between the surface bump and the through electrode.

6. The semiconductor device according to claim 1 , wherein the semiconductor device includes a reverse bump for external connection disposed at an end on a reverse surface side of the through electrode.

7. The semiconductor device according to claim 1 , wherein the through electrode is formed in a cylindrical shape.

8. The semiconductor device according to claim 1 , wherein the surface of the semiconductor substrate includes a device-forming surface on which a plurality of semiconductor devices are formed.

9. An electronic component comprising:
an interposer having a plurality of outside terminals on a reverse surface thereof;
the semiconductor device of claim 1 laid on a surface of the interposer in a posture in which the surface of the interposer is directed upwardly;
a second semiconductor device having a plurality of reverse bumps and laid on the surface of the semiconductor device so that the reverse bumps are electrically connected to the through electrode; and
a resin package sealing the semiconductor device and the second semiconductor device.

10. An electronic component comprising:
an interposer having a plurality of outside terminals on a reverse surface thereof;
the semiconductor device of claim 1 laid on a surface of the interposer in a posture in which the surface of the semiconductor substrate is directed upwardly;
a second semiconductor device having a plurality of reverse bumps and laid on the surface of the semiconductor device so that the reverse bumps are electrically connected to the through electrode; and
a resin package sealing the semiconductor device and the second semiconductor device.

11. A semiconductor device comprising:
a semiconductor substrate;
a gate insulating film formed on a surface of the semiconductor substrate;
an interlayer insulating film formed on the gate insulating film;
a surface electrode including a plurality of wiring lines having a damascene structure selectively embedded in the interlayer insulating film with a predetermined pattern and a between-wiring-lines insulating film disposed between the wiring lines adjoining each other, a part of the interlayer insulating film forming the between-wiring-lines insulating film;
a through electrode penetrating the semiconductor substrate and electrically connected to the surface electrode; and
a via insulating film disposed between the through electrode and the semiconductor substrate,
wherein the wiring lines and the between-wiring-lines insulating film are formed to be flush with each other in a connection surface of the wiring lines and the between-wiring-lines insulating film with the through electrode,
wherein the surface electrode further includes
a facing portion facing the through electrode,
a projecting portion projecting in a lateral direction from the facing portion, and
an insulating layer embedded in the surface of the semiconductor substrate and having a same pattern as the between-wiring-lines insulating film which forms the projecting portion.

12. The semiconductor device according to claim 11 , wherein the wiring lines and the between-wiring-lines insulating film are alternately arranged in a stripe manner in the surface electrode.

Assignees

• Rohm Co Ltd

Inventors

• Mitsuhashi Toshiro

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9226

  with via interconnections · CPC title