Operation method of nonvolatile memory system

Patent metadata

Field	Value
Publication number	US-9478300-B2
Application number	US-201514883922-A
Country	US
Kind code	B2
Filing date	Oct 15, 2015
Priority date	Nov 24, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An operation method of a nonvolatile memory system in accordance with example embodiments of inventive concepts includes detecting an on-cell count of the memory cells using a sampling start voltage, comparing the detected on-cell count with a reference value, setting a plurality of sampling voltages based on the comparison result, performing a sampling operation with respect to the memory cells using the sampling voltages, and detecting an optimum read voltage for distinguishing any one program state among the program states based on a result of the sampling operation.

First claim

What is claimed is:

1. An operation method of a nonvolatile memory system including a memory controller configured to control a nonvolatile memory,
wherein the nonvolatile memory device comprises a three-dimensional memory cell array including a plurality of memory blocks each comprising a plurality of cell strings, each of cell strings comprises a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor disposed between the memory cells and the substrate, and a string selection transistor disposed between the memory cells and a bitline,
the operation method comprises:
performing a cell-counting operation on selected memory cells of the plurality of memory cells to detect a cell count;
comparing the detected cell count with a reference value;
setting a plurality of sampling voltages based on a result of the comparison;
performing a sampling operation with respect to the selected memory cells using the plurality of sampling voltages; and
performing a read operation on the selected memory cells based on a result of the sampling operation.

2. The operation method of claim 1 , wherein the cell-counting operation includes:
reading data from the selected memory cells;
detecting and correcting an error of the read data; and
detecting the cell count of the selected memory cells using a sampling start voltage of the plurality of sampling voltages if the error of the read data is not corrected.

3. The operation method of claim 1 , wherein the setting a plurality of sampling voltages based on a result of the comparison includes:
setting the plurality of sampling voltages lower than a sampling start voltage if the detected cell count is greater than the reference value, or
setting the plurality of sampling voltages higher than the sampling start voltage if the detected cell count is not greater than the reference value.

4. The operation method of claim 3 , wherein the performing the sampling operation includes:
generating a plurality of sample data by performing the sampling operation on the selected memory cells using the plurality of sampling voltages; and
detecting first through third values using the generated sample data.

5. The operation method of claim 4 , wherein the performing the sampling operation further includes:
comparing the first through third values; and
performing an additional sampling operation on the selected memory cells or detecting an optimum read voltage for distinguishing any one program state among a plurality of program states of the plurality of memory cells based on the result of the sampling operation.

6. The operation method of claim 5 , wherein the sampling voltages include the sampling start voltage and first through third sampling voltages,
wherein the detecting the first through third values includes detecting the first value using the lowest two sampling voltages among the sampling start voltage and the first through third sampling voltages and detecting the third value using the highest two sampling voltages among the sampling start voltage and the first through third sampling voltages, and
wherein the performing the additional sampling operation on the memory cells or the detecting the optimum read voltage includes the detecting the optimum read voltage if the second value is smaller than the first and third values, and the performing the additional sampling operation if the second value is not smaller than the first and third values.

7. The operation method of claim 6 , wherein the detecting optimum read voltage is performed using a regression analysis.

8. The operation method of claim 5 , wherein the performing a read operation on the selected memory cells comprises reading data stored in the selected memory cells using the optimum read voltage.

9. The operation method of claim 1 , wherein
the memory cells have a plurality of program states, and
the reference value has a different value depending on each of the program states of the selected memory cells.

10. The operation method of claim 1 , wherein
the memory cells have a plurality of program states, and
the reference value corresponds to a number of memory cells turned-on by an optimum read voltage with respect to each of the program states.

11. The operation method of claim 2 , wherein the data stored in the selected memory cells is randomized data.

12. An operation method of a storage device,
wherein the storage device includes a three-dimensional memory cell array including a plurality of memory blocks each comprising a plurality of cell strings, each of cell strings comprises a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor disposed between the memory cells and the substrate, and a string selection transistor disposed between the memory cells and a bitline,
the operation method comprises:
detecting first through third values by sampling selected memory cells of the plurality of memory cells using first through fourth sampling voltages;
comparing the first through third values;
comparing a cell count corresponding to any one sampling voltage among the first through fourth sampling voltages with a reference value, based on a result of the comparing the first through third values;
performing an additional sampling operation on the selected memory cells based on a result of the comparing the cell count and the reference value; and
performing a read operation on the memory cells based on a result of the additional sampling operation.

13. The operation method of claim 12 , wherein
the first sampling voltage is smaller than the second sampling voltage, the second sampling voltage is smaller than the third sampling voltage, the third sampling voltage is smaller than the fourth sampling voltage, and
the detecting first through third values includes determining the first value based on a number of memory cells having a threshold voltage between the first and second sampling voltages, determining the second value based on a number of memory cells having a threshold voltage between the second and third sampling voltages, determining the third value based on a number of memory cells having a threshold voltage between the third and fourth sampling voltages, among the selected memory cells.

14. The operation method of claim 13 , wherein the comparing the first through third values includes determining whether the second value is smaller than the first and third values.

15. The operation method of claim 14 , wherein the comparing the cell count with the reference value includes comparing the cell count with the reference value if the second value is not smaller than the first and third values.

16. An operation method of a nonvolatile memory device,
wherein the nonvolatile memory device comprises a three-dimensional memory cell array including a plurality of memory blocks each comprising a plurality of cell strings, each of cell strings comprises a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor disposed between the memory cells and the substrate, and a string selection transistor disposed between the memory cells and a bitline,
the operation method comprises:
performing a cell counting operation on selected memory cells of the plurality of memory cells to detect a cell count;
comparing the detected cell count with a reference value;
performing a sampling operation on the selected memory cells based on a result of comparison;
the sampling operation including setting first to third sampling voltages in one

Assignees

• Kim Kwanghoon
• Yoo Younggeon
• Kong Junjin
• Samsung Electronics Co Ltd

Inventors

• Kim Kwanghoon
• Yoo Younggeon
• Kong Junjin

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title