Non-volatile memory express (NVMe) device power management

Patent metadata

Field	Value
Publication number	US-9477295-B2
Application number	US-201414279118-A
Country	US
Kind code	B2
Filing date	May 15, 2014
Priority date	May 15, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU); a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU; a service processor operably coupled to the CPU and to the NVMe; and a memory operably coupled to the service processor, the memory including program instructions stored thereon that, upon execution by the service processor, cause the service processor to: receive performance data from the CPU, receive metrics data from a source other than the CPU, and control an amount of power provided to the NVMe device based, at least in part, upon the performance data and the metrics data.

First claim

The invention claimed is:

1. An Information Handling System (IHS), comprising:
a Central Processing Unit (CPU);
a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU;
a service processor operably coupled to the CPU and to the NVMe; and
a memory operably coupled to the service processor, the memory including program instructions stored thereon that, upon execution by the service processor, cause the service processor to:
receive performance data from the CPU, the performance data including an aggregated read/write volume of root ports in a PCIe bus;
receive metrics data from a source other than the CPU, the metrics data including a volume of input/output (I/O) usage for a PCI slot collected from a bus controller and a volume of read and write operations recorded by a software application;
assign a respective weight to the performance data and to each of metrics data; and

control an amount of power provided to the NVMe device, at least in part, by calculating a weighed average of the performance data and the metrics data using the respective weights, and mapping the weighed average to a power cap for the NVMe device.

2. The IHS of claim 1 , wherein the NVMe includes a Peripheral Component Interconnect Express (PCIe) solid-state drive (SSD).

3. The IHS of claim 1 , wherein the service processor includes a Baseboard Management Controller (BMC).

4. The IHS of claim 1 , wherein the performance data includes a status of a free running counter.

5. The IHS of claim 1 , wherein the performance data includes bandwidth utilization.

6. The IHS of claim 1 , wherein the metrics data includes an overall power budget of the IHS.

7. The IHS of claim 1 , wherein the metrics data includes a read and write statistic of the NVMe device obtained via a Management Component Transport Protocol (MCTP) interface.

8. The IHS of claim 1 , wherein the metrics data includes a time of the day.

9. The IHS of claim 1 , wherein to control the amount of power the program instructions are configured to cause the service processor to put a limit, via a sideband or out-of-band channel, upon a maximum amount of power that can be drawn by the NVMe device.

10. The IHS of claim 1 , wherein to control the amount of power the program instructions are configured to cause the service processor to determine that it is in charge of managing power provided to the NVMe device based upon a Basic Input/Output System (BIOS) token.

11. A method, comprising:
receiving performance data from a Central Processing Unit (CPU), the performance data including an aggregated read/write volume of root ports in a PCIe bus;
receiving metrics data from a source other than the CPU, the metrics data including a volume of input/output (I/O) usage for a PCI slot collected from a bus controller and a volume of read and write operations recorded by a software application;
assigning a respective weight to each of the performance data and the metrics data; and
controlling, via a sideband or out-of-band channel, an amount of power provided to a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU, at least in part, by calculating a weighed average of the performance data and the metrics data using the respective weights, and mapping the weighed average to a power cap for the NVMe device.

12. The method of claim 11 , wherein the NVMe includes a Peripheral Component Interconnect Express (PCIe) solid-state drive (SSD) coupled to the CPU via a PCIe bus, and wherein the service processor includes a Baseboard Management Controller (BMC).

13. The method of claim 11 , wherein the performance data includes a status of a free running counter or bandwidth utilization.

14. The method of claim 11 , wherein the metrics data further includes an overall power budget, a read and write statistic of the NVMe device obtained via a Management Component Transport Protocol (MCTP) interface, or a time of the day.

15. The method of claim 11 , wherein controlling the amount of power includes limiting a maximum amount of power that can be drawn by the NVMe device based upon a Basic Input/Output System (BIOS) indication.

16. A non-transitory computer-readable medium having program instructions stored thereon that, upon execution by a Baseboard Management Controller (BMC) within an Information Handling System (IHS), cause the BMC to:
determine an input/output (I/O) workload running on a given Peripheral Component Interconnect Express (PCIe) solid-state drive (SSD), the I/O workload including a random read operation, a sequential read operation, a random write operation, and a sequential write operation;
assign a respective weight to each given operation of the I/O workload indicating a relative power consumption of the given operation with respect to a power consumption of the random read operation; and
control, via a sideband or out-of-band channel, an amount of power provided to the PCIe SSD, at least in part, by calculating a weighed average of the operations using the respective weights, and multiplying a total power available to the PCIe SSD by the weighed average.

17. The non-transitory computer-readable medium of claim 16 , wherein the components are weighed such that the sequential read component has twice the weight of the random read component, the sequential write component has twice the weight of the random read component, and the random write component has five times the weight of the random read component.

Assignees

• Dell Products Lp

Inventors

• Jreji Elie Antoun
• Bolen Austin P
• V Karthik

Classifications

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3268

  Power saving in hard disk drive · CPC title

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title