Efficient integrated switching voltage regulator

Patent metadata

Field	Value
Publication number	US-9477291-B2
Application number	US-201514634481-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Jun 29, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

First claim

We claim:

1. An integrated circuit comprising:
a switching voltage regulator (SVR)-comprising one or more bridge drivers to provide regulated power supply to a plurality of power domains, the one or more bridge drivers comprising one or more transistors that act as switches of the SVR; and
a power control unit (PCU) operable to adjust switching frequencies of the one or more bridge drivers of the SVR according to states of the plurality of power domains, wherein at least one of a drive strength and an active phase count of the one or more bridge drivers is adjusted by a logic unit of the SVR when at least one of the switching frequencies of the SVR is adjusted.

2. The integrated circuit of claim 1 further comprises a memory unit to store switching frequencies for the plurality of power domains.

3. The integrated circuit of claim 1 , wherein the PCU is operable to access the memory unit when a state of any one of the states of the plurality of power domains changes.

4. The integrated circuit of claim 1 , wherein the memory unit is part of the PCU.

5. The integrated circuit of claim 1 , wherein the memory unit is accessible by software or hardware to adjust values of the switching frequencies for the plurality of power domains.

6. The integrated circuit of claim 1 , wherein the power domains are associated with different parts of the integrated circuit including at least one of:
one or more processing cores,
one or more cache units,
one or more input-output (I/O) drivers, or
one or more graphics units.

7. The integrated circuit of claim 1 , wherein the voltage regulator is a DC-DC buck type multiphase converter.

8. The integrated circuit of claim 1 , wherein the states include P-states and C-states associated with the plurality of power domains.

9. The integrated circuit of claim 1 further comprises a memory unit to store switching frequencies associated with P-states and switching frequencies associated with C-states.

10. The integrated circuit of claim 1 , wherein the PCU is operable to adjust the switching frequencies to cause the SVR to operate with substantially minimum SVR losses.

11. The integrated circuit of claim 1 , wherein the PCU is operable to adjust switching frequencies of the SVR by dynamically selecting an output signal having multiple phases from a divider of the SVR.

12. The integrated circuit of claim 11 , wherein the SVR comprises a phase slope shaper operable to receive the output signal selected from the divider, the phase slope shaper to generate a signal corresponding to the output signal but with adjusted slope.

13. The integrated circuit of claim 11 , wherein the phase slope shaper is operable to reduce slope of the signal when frequency of the output signal increases, and wherein the phase slope shaper circuit is operable to decrease slope of the signal when frequency of the output signal increases.

14. The integrated circuit of claim 11 , wherein the phase slope shaper is coupled to a switch matrix comprising the one or more switches via a phase selection stage.

15. The integrated circuit of claim 14 , wherein the switch matrix is operable to generate a triangular wave signal according to the signal received from the phase slope shaper.

16. The integrated circuit of claim 14 further comprises multiplexers coupled to the phase slope shaper and the switch matrix.

17. The integrated circuit of claim 1 , wherein the one or more bridge drivers of the SVR have adjustable drive strengths which are adjusted when any state of the plurality of power domains changes.

18. The integrated circuit of claim 1 , wherein the logic unit to adjust drive strengths of the one or more bridge drivers to cause the SVR to operate with substantially minimum SVR losses.

19. A computer system comprising:
a memory;
a processor coupled to the memory, the processor comprising a switching voltage regulator (SVR)-comprising one or more bridge drivers to provide regulated power supply to a plurality of power domains, the one or more bridge drivers comprising one or more transistors that act as switches of the SVR; and
a power control unit (PCU) operable to adjust switching frequencies of the one or more bridge drivers of the SVR according to states of the plurality of power domains, wherein at least one of a drive strength and an active phase count of the one or more bridge drivers is adjusted by a logic unit of the SVR when at least one of the switching frequencies of the SVR is adjusted; and

a wireless interface for communicatively coupling the processor with other devices.

20. The computer system of claim 19 , wherein the processor includes a plurality of processing cores, each processing core associated with a power domain from the plurality of power domains.

21. The computer system of claim 19 further comprises a display unit communicatively coupled to the processor.

Assignees

• Intel Corp

Inventors

• Sizikov Gregory
• Zelikson Michael
• Rotem Efraim
• Fayneh Eyal

Classifications

• G06F1/32

  Means for saving power · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F3/08

  wherein the variable is DC · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title