Memory array clock gating scheme
US-9158328-B2 · Oct 13, 2015 · US
Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time
US9477258B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9477258-B2 |
| Application number | US-201414509055-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 8, 2014 |
| Priority date | May 22, 2013 |
| Publication date | Oct 25, 2016 |
| Grant date | Oct 25, 2016 |
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Abstract
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A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
First claim
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What is claimed is: 1. A clock tree in a circuit, comprising: a first sub clock tree, disposed in a first function module of the circuit to transfer a first delayed clock to different components in the first function module; a second sub clock tree, disposed in a second function module of the circuit to transfer a second delayed clock to different components in the second function module; at least one first channel power-mode-aware buffer connected in series between the first…
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- G06F1/10Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9477258B2 cover?
- A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provid…
- Who is the assignee on this patent?
- Ind Tech Res Inst, Univ Chung Yuan Christian, Nat Univ Tsing Hua
- What technology area does this patent fall under?
- Primary CPC classification G06F1/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Oct 25 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).