Electrodeposited nano-twins copper layer and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9476140-B2
Application number	US-201213679154-A
Country	US
Kind code	B2
Filing date	Nov 16, 2012
Priority date	Nov 16, 2011
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.

First claim

What is claimed is:

1. An electrodeposited nano-twins copper metal layer, wherein over 50% of a volume of the nano-twins copper metal layer comprises a plurality of crystal grains, each of the plurality of crystal grain is connected with one another, and each crystal grain is formed as a result of the plurality of nano-twins working to stack in the orientation of the [111] crystal axis, for which an angle included between neighboring crystal grains is 0° to 20°, and each crystal grain has a diameter of 1 μm-10 μm,
wherein a [111] surface of the nano-twins is exposed on over 50% of a surface of the nano-twins copper metal layer.

2. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein the nano-twins copper metal layer further comprises a seed layer, which takes up 1% to 50% of the volume of the nano-twins copper metal layer.

3. The electrodeposited nano-twins copper metal layers according to claim 1 , wherein a thickness of the nano-twins copper metal layer is 0.1 μm-500 μm.

4. The electrodeposited nano-twins copper metal layer according to claim 3 , wherein the thickness of the nano-twins copper metal layer is 0.8 μm-200 μm.

5. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein at least 50% of the crystal grains has a longitudinal axis, for which the longitudinal axis denotes the stacking direction for nano-twins, the twins copper metal layer has a thickness direction, for which the thickness direction is normal to a surface of the twins copper metal layer, an angle included between the [111] crystal axis and the longitudinal axis is 0° to 20°, and a longitudinal axis direction of the crystal grain is essentially the same as the thickness direction of the twins metal layer.

6. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein at least 90% of a surface of the nano-twins copper layer is [111] surface.

7. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein all surfaces of the nano-twins copper metal layer are [111] surface.

8. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein at least 70% of the crystal grains is formed as a result of stacking of the plurality of nano-twins.

9. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein the crystal grains further includes in between themselves impure crystal grains.

10. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein the thickness of the crystal grain is in a range of 0.01 μm-500 μm.

11. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein the thickness of the crystal grain is in a range of 0.1 μm-200 μm.

12. The electrodeposited nano-twins copper metal layer according to claim 1 , wherein the nano-twins copper metal layer is used in through silicon via (TSV), semiconductor chip interconnect, packaging substrate pin through hole, metal interconnect, or substrate circuit.

13. A substrate having nano-twins copper metal layer, comprising:
a substrate; and
the electrodeposited nano-twins copper metal layer according to claim 1 , which is arranged inside, or on the surface of the substrate.

14. The substrate having nano-twins copper metal layer according to claim 13 , wherein the substrate is selected from a group consisting of silicon substrate, glass substrate, quartz substrate, metal substrate, plastic substrate, printed circuit substrate, III-V group material substrate, and a combination thereof.

Assignees

• Univ Nat Chiao Tung

Inventors

• Chen Chih
• Tu King-Ning
• Liu Taochi

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• C25D3/38 Primary

  of copper · CPC title

• C30B7/12 Primary

  by electrolysis · CPC title