ASIC element, in particular as a component of a vertically integrated hybrid component

Patent metadata

Field	Value
Publication number	US-9475693-B2
Application number	US-201514732998-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	Jun 6, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

First claim

What is claimed is:

1. An ASIC element, comprising:
an ASIC substrate into which electrical circuit functions are integrated;
and an ASIC layer structure disposed on the ASIC substrate and including:
multiple wiring levels for the circuit functions, the multiple wiring levels including at least one lower wiring level and at least one upper wiring level;
insulation layers that separate the wiring levels from one another;
metallic plugs for interconnecting the circuit functions;
and at least one connecting area in at least one of the upper most wiring levels,
wherein at least one chain is formed by an arrangement of the metallic plugs arranged vertically in a direct line and is implemented in the ASIC layer structure below the connecting area, and at least one of the at least one chain is a complete chain extending from the at least one of the upper wiring levels to the ASIC substrate;
at least one of the at least one chain ends directly on an insulation trench formed at a surface of the ASIC substrate.

2. The ASIC element as recited in claim 1 , further comprising at least one layer area provided below the at least one connecting area in a layout of the wiring levels of the ASIC layer structure, wherein the at least one layer area forms at least one intermediate land for the metallic plugs of the at least one chain.

3. The ASIC element as recited in claim 1 , wherein:
at least one of the at least one chain is a partial chain that extends over multiple ones of the wiring levels, but does not extend through the entire ASIC layer structure from the at least one of the upper wiring levels down to the ASIC substrate.

4. The ASIC element as recited in claim 1 , wherein the at least one chain is situated such that, when viewed from a plane above the connecting area, the chains are spaced in a two-dimensional grid that extends at least over a part of the connecting area.

5. The ASIC element as recited in claim 1 , wherein the at least one chain is used as an electrical connection.

6. The ASIC element as recited in claim 1 , wherein the at least one chain has an exclusively mechanical function.

7. The ASIC element as recited in claim 1 , wherein the plugs are made of at least one of tungsten and copper.

8. A vertically integrated hybrid component, comprising: an ASIC element that includes:
an ASIC substrate into which electrical circuit functions are integrated;
an ASIC layer structure disposed on the ASIC substrate and including:
multiple wiring levels for the circuit functions;
insulation layers that separate the wiring levels from one another;
metallic plugs for interconnecting the circuit functions;
and at least one connecting area in an uppermost one of the uppermost wiring levels, which is farthest, of the wiring levels, away from the ASIC substrate;
and a further element connected, via a bonding connection in the at least one connecting area, to the ASIC layer structure;
wherein:
at least one chain is formed by an arrangement of the metallic plugs arranged vertically in a direct line below the connecting area;
at least one of the at least one chain is a complete chain extending from the uppermost wiring level to the ASIC substrate;
at least one of the at least one chain ends directly on an insulation trench formed at a surface of the ASIC substrate.

9. The vertically integrated hybrid component as recited in claim 8 , wherein the further element includes a MEMS element, the MEMS element having a functional component that is hermetically sealed by the bonding connection to the ASIC element and is electrically connected to the ASIC element.

Assignees

• Bosch Gmbh Robert

Inventors

• Meisel Daniel Christoph
• Schelling Christoph
• Kramer Torsten
• Frey Jens

Classifications

• B81C1/00238 Primary

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title