Frequency dividing apparatus and related method

Patent metadata

Field	Value
Publication number	US-9473147-B2
Application number	US-201514636190-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	Mar 3, 2015
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

First claim

What is claimed is:

1. A frequency dividing apparatus, comprising:
a plurality of latching devices, arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and
a controlling device, arranged to generate the first reset signal at least according to a programming input signal;

wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

2. The frequency dividing apparatus of claim 1 , wherein input clock signal has a third oscillating frequency, the first oscillating frequency is substantially a half of the third oscillating frequency, and the second oscillating frequency is substantially a third of the third oscillating frequency.

3. The frequency dividing apparatus of claim 1 , further comprising:
a conducting path, directly connected between the first latching device and the controlling device for conducting the first reset signal from the controlling device to the first latching device.

4. The frequency dividing apparatus of claim 1 , wherein the controlling device generates the first reset signal further according to a mode control signal and the output signal.

5. The frequency dividing apparatus of claim 1 , wherein a second reset signal is arranged to reset the controlling device, and the second reset signal is an inverse signal of the first reset signal.

6. The frequency dividing apparatus of claim 5 , further comprising:
a conducting path, directly connected between an output terminal of the controlling device and an input terminal of the controlling device for conducting the second reset signal from the output terminal to the input terminal.

7. The frequency dividing apparatus of claim 1 , wherein the plurality of latching devices comprises:
the first latching device, having a clock terminal receiving the input clock signal, a reset terminal receiving the first reset signal, a data input terminal receiving the output signal, and a data output terminal outputting a first latching signal; and
a second latching device, having a clock terminal receiving an inverse input clock signal of the input clock signal, a data input terminal receiving the first latching signal, a first data output terminal outputting a second latching signal, and a second data output terminal outputting the output signal.

8. The frequency dividing apparatus of claim 7 , wherein the first reset signal resets the first latching device to make the first latching signal kept intact for substantially one period of the input clock signal.

9. The frequency dividing apparatus of claim 7 , wherein the controlling device comprises:
a first AND gate, having a first input terminal receiving the second latching signal, a second input terminal receiving a mode control signal, and an output terminal outputting a first logical signal;
a third latching device, having a clock terminal receiving the input clock signal, a data input terminal receiving the first logical signal, and a first data output terminal outputting a third latching signal;
a second AND gate, having a first input terminal receiving the third latching signal, a second input terminal receiving the programming input signal, and an output terminal outputting a second logical signal; and
a fourth latching device, having a clock terminal receiving the inverse input clock signal of the input clock signal, a data input terminal receiving the second logical signal, and a first data output terminal outputting the first reset signal.

10. The frequency dividing apparatus of claim 9 , further comprising:
a conducting path, directly connected between the reset terminal of the first latching device and the first data output terminal of the fourth latching device for conducting the first reset signal to the first latching device.

11. The frequency dividing apparatus of claim 9 , wherein the fourth latching device further comprises a second data output terminal for outputting a second reset signal, the second reset signal is an inverse signal of the first reset signal, and the second reset signal is arranged to reset the first AND gate to make the plurality of latching devices generate the output signal having the first oscillating frequency.

12. The frequency dividing apparatus of claim 11 , further comprising:
a conducting path, directly connected between the second data output terminal of the fourth latching device and a third input terminal of the first AND gate for conducting the second reset signal to the first AND gate.

13. A frequency dividing method, comprising:
using a plurality of latching devices to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal;
generating the first reset signal at least according to a programming input signal; and
using the first reset signal to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.

14. The frequency dividing method of claim 13 , wherein input clock signal has a third oscillating frequency, the first oscillating frequency is substantially a half of the third oscillating frequency, and the second oscillating frequency is substantially a third of the third oscillating frequency.

15. The frequency dividing method of claim 13 , further comprising:
using a conducting path to directly conduct the first reset signal to the first latching device.

16. The frequency dividing method of claim 13 , wherein the first reset signal is generated further according to a mode control signal and the output signal.

Assignees

• Mediatek Inc

Inventors

• Chiu Wei-Hao
• Lin Ang-Sheng
• Wang Kun-Yin

Classifications

• H03K21/38

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

• H03K23/667 Primary

  by switching the base during a counting cycle · CPC title