Input switch leakage compensation

Patent metadata

Field	Value
Publication number	US-9473085-B2
Application number	US-201414491817-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 9, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

An apparatus including: a first switch configured to provide a feed-forward path at an input of a first amplifier of a plurality of amplifiers coupled together at a single port, the feed-forward path configured to substantially reduce a leakage current into an input of a second amplifier of the plurality of amplifiers.

First claim

What is claimed is:

1. An apparatus comprising:
a bias circuit configured to provide a bias voltage to a plurality of amplifiers, inputs of the plurality of amplifiers are coupled to a single port; and
a first switch configured to direct a leakage current away from an input of a first amplifier of the plurality of amplifiers through a bypass path from an output of the bias circuit to an input of a second amplifier of the plurality of amplifiers.

2. The apparatus of claim 1 , each of the plurality of amplifiers includes a low noise amplifier.

3. The apparatus of claim 1 , the bias voltage is a DC bias voltage.

4. The apparatus of claim 1 , the first amplifier is an operating mode and the second amplifier is in an idle mode.

5. The apparatus of claim 4 , further comprising
a second switch coupled to the second amplifier, the second switch configured to ground the input of the second amplifier.

6. The apparatus of claim 1 , further comprising
a third amplifier coupled to the single port.

7. The apparatus of claim 1 , further comprising
third and fourth switches configured to connect the single port to the input of the second amplifier.

8. The apparatus of claim 7 , wherein the bypass path is coupled to a connection point between the third and fourth switches.

9. The apparatus of claim 8 , wherein the first switch is configured to connect the bias circuit to the connection point when the third and fourth switches are in open states.

10. The apparatus of claim 7 , further comprising
fifth and sixth switches configured to connect the single port to the input of the first amplifier.

11. The apparatus of claim 10 , the first amplifier is an idle mode and the second amplifier is in an operating mode.

12. The apparatus of claim 11 , further comprising
a seventh switch coupled to the first amplifier, the seventh switch configured to ground the input of the first amplifier.

13. An apparatus comprising:
means for biasing first and second amplifiers, inputs of the first and second amplifiers are coupled to a single port; and
means for directing a leakage current away from an input of the first amplifier through a bypass path from an output of the means for biasing to an input of the second amplifier.

14. The apparatus of claim 13 , further comprising
means for grounding the input of the second amplifier.

15. The apparatus of claim 13 , further comprising
means for connecting the single port to the input of the second amplifier.

16. The apparatus of claim 15 , the means for directing is configured to connect the bypass path at the means for connecting.

17. The apparatus of claim 13 , further comprising
means for connecting the single port to the input of the first amplifier.

18. The apparatus of claim 13 , further comprising
means for grounding the input of the first amplifier.

19. An apparatus comprising:
a plurality of amplifiers, inputs of the plurality of amplifiers are coupled to a single port;
a bias circuit configured to provide a bias voltage to plurality of amplifiers; and
a first switch configured to direct a leakage current away from an input of a first amplifier of the plurality of amplifiers through a bypass path from an output of the bias circuit to an input of a second amplifier of the plurality of amplifiers.

20. The apparatus of claim 19 , further comprising
second and third switch coupled to the input of the second amplifier,
the first switch coupled to a connection point between the second switch and the third switch.

21. The apparatus of claim 19 , wherein the apparatus is a receiver.

Assignees

• Qualcomm Inc

Inventors

• Lakdawala Hasnain Mohammedi
• Choksi Ojas Mahendra
• Fan Bin

Classifications

• H03F1/223

  with MOSFET's · CPC title

• H03F2203/21109

  An input signal being distributed by switching to a plurality of paralleled power amplifiers · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H04B1/0053

  with common antenna for more than one band · CPC title