Integration of area efficient antennas for phased array or wafer scale array antenna applications

Patent metadata

Field	Value
Publication number	US-9472859-B2
Application number	US-201414281951-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	May 20, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

First claim

We claim:

1. A package structure, comprising:
an RFIC (radio frequency integrated circuit) chip;
an antenna package comprising a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element; and
an electrical interface between the antenna package and the RFIC chip, wherein the electrical interface comprises micro via joints, wherein the micro via joints are formed within a BEOL (back end of line) structure of the RFIC chip, and wherein the micro via joints provide electrical connections between wiring of the BEOL structure and metallization on the second surface of the glass substrate,
wherein a backside surface of the RFIC chip is directly bonded to the ground plane on the second surface of the glass substrate of the antenna package using a layer of adhesive material.

2. The package structure of claim 1 , wherein the at least one planar antenna element comprises a plurality of planar antenna elements forming an antenna array.

3. The package structure of claim 1 , wherein the glass substrate is a glass wafer, and wherein the RFIC chip is an element of a semiconductor wafer comprising multiple chips, wherein the glass wafer and semiconductor wafer are bonded together to form an integral package.

4. A package structure, comprising:
an RFIC (radio frequency integrated circuit) chip; and
an antenna package comprising a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element,
wherein the antenna package is bonded to the RFIC chip using a layer of adhesive material,
wherein the RFIC chip comprises a silicon-on insulator (SOI) substrate, wherein the SOI substrate comprises a silicon layer in which active devices are formed, and a buried insulating layer, wherein a backside surface of the RFIC chip is etched to expose the buried insulating layer, and wherein the antenna package is bonded to the buried insulating layer of the SOI substrate.

5. The package structure of claim 4 , wherein the at least one planar antenna element comprises a plurality of planar antenna elements forming an antenna array.

6. The package structure of claim 4 , wherein the glass substrate is a glass wafer, and wherein the RFIC chip is an element of a semiconductor wafer comprising multiple chips, wherein the glass wafer and semiconductor wafer are bonded together to form an integral package.

7. A wireless communications device, comprising:
an RFIC (radio frequency integrated circuit) chip; and
an antenna package comprising a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element, wherein the antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material; and
an application board, wherein the RFIC chip is mounted to the application board;
wherein the RFIC chip comprises a silicon-on insulator (SOI) substrate, wherein the SOI substrate comprises a silicon layer in which active devices are formed, and a buried insulating layer, wherein a backside surface of the RFIC chip is etched to expose the buried insulating layer, and wherein the antenna package is bonded to the buried insulating layer of the SOI substrate.

8. The wireless communications device of claim 7 , wherein the at least one planar antenna element comprises a plurality of planar antenna elements forming an antenna array.

9. The wireless communications device of claim 7 , wherein the glass substrate is a glass wafer, and wherein the RFIC chip is an element of a semiconductor wafer comprising multiple chips, wherein the glass wafer and semiconductor wafer are bonded together to form an integral package.

10. The wireless communications device of claim 7 , wherein the RFIC chip is bonded to the application board using an array of C4 solder ball connections.

11. The wireless communications device of claim 7 , wherein the glass substrate is a glass material having a dielectric constant of about 4.0.

12. The wireless communications device of claim 7 , wherein the wireless communications device is configured to operate at a millimeter wave frequency range or higher.

Assignees

• IBM

Inventors

• Dang Bing
• Liu Duixian
• Plouchart Jean-Olivier
• Sorce Peter Jerome
• Tsang Cornelia Kang-I

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title