Isolated semiconductor layer over buried isolation layer

US9472571B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9472571-B2
Application numberUS-201414301848-A
CountryUS
Kind codeB2
Filing dateJun 11, 2014
Priority dateApr 13, 2014
Publication dateOct 18, 2016
Grant dateOct 18, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising silicon-based single-crystal semiconductor material; forming an isolation recess in the substrate; forming sidewall insulators at sides of the isolation recess; forming a buried isolation layer of thermal oxide at least 100 nanometers thick at a bottom of the isolation recess by a thermal oxidation process, so that the buried isolation layer does not extend up along interior lateral surfaces of the sidewall insulators, a top surface of the buried isolation layer being lower than a top surface of the substrate adjacent to the isolation recess; and forming an isolated semiconductor layer over the buried isolation layer and separated from the substrate at lateral surfaces of the substrate above the buried isolation layer by the sidewall insulators, a top surface of the isolated semiconductor layer being substantially coplanar with the a top surface of the substrate adjacent to the buried isolation layer; wherein the step of forming the isolated semiconductor layer comprises the steps: forming a seed layer of single-crystal silicon-based semiconductor material on the top surface of the substrate by an epitaxy process; forming a layer of polysilicon over the top surface of the substrate, contacting the seed layer and extending into the isolation recess over the buried isolation layer; and performing a radiant-induced recrystallization process which heats the polysilicon so as to crystallize the polysilicon to form a single-crystal semiconductor layer over the buried isolation layer. 2. The method of claim 1 , wherein the step of forming the isolated semiconductor layer further comprises planarizing the single-crystal semiconductor layer down to a stop layer over the top surface of the substrate.

Assignees

Inventors

Classifications

  • Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

  • using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • of semiconductor materials · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

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Frequently asked questions

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What does patent US9472571B2 cover?
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed …
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10P90/1912. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 18 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).