Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9472297-B2
Application number	US-201514724543-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Dec 19, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A semiconductor memory device includes a memory cell part including a main memory unit and a redundancy memory unit, a page buffer circuit including a plurality of page buffer groups and reading data stored in the memory cell part, and a sensing circuit including a plurality of sense amplifiers corresponding to the plurality of page buffer groups, respectively, and suitable for sensing the read data, wherein the plurality of sense amplifiers perform data sensing operations in parallel in order to sense the read data.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a main sense amplifier circuit suitable for sensing first potentials of main data lines coupled to a main cell region and outputting the first potentials to a global data line in response to first strobe signals having a first period; and
a redundancy sense amplifier circuit suitable for sensing a second potential of a redundancy data line coupled to a redundancy cell region and outputting the second potential to the global data line in response to second strobe signals having a second period,
wherein the second period is shorter than the first period.

2. The semiconductor memory device of claim 1 , wherein:
the main cell region includes a main memory unit and a plurality of main page buffer groups corresponding thereto; and
the plurality of main page buffer groups correspond to the main data lines, respectively, and output data read from the main memory unit to the main data lines in response to first column selection signals.

3. The semiconductor memory device of claim 2 , wherein:
the redundancy memory area includes a redundancy memory unit and a redundancy page buffer group corresponding thereto;
the redundancy page buffer group is coupled to the redundancy data line and outputs data read from the redundancy memory unit to the redundancy data line in response to second column selection signals; and
the first column selection signals have the first period, and the second column selection signals have the second period.

4. The semiconductor memory device of claim 3 , further comprising:
a column selection signal and strobe signal generation unit suitable for generating the first and second strobe signals and the first and second column selection signals.

5. The semiconductor memory device of claim 4 , wherein the column selection signal and strobe signal generation unit controls a data output operation time of each of the redundancy page buffer group and the redundancy sense amplifier circuit by controlling periods of the second strobe signals and the second column selection signals.

6. A semiconductor memory device, comprising:
a memory block including a main memory area and a redundancy memory area;
main data lines and a redundancy data line corresponding to the main memory area and the redundancy memory area, respectively;
a strobe signal generation unit suitable for outputting first strobe signals having a first period and a second strobe signal having a second period; and
a sense amplifier circuit suitable for sensing potential levels of the main data lines and the redundancy data line and outputting sensed read data to a global data line in response to the first and second strobe signals.

7. The semiconductor memory device of claim 6 , wherein the second period is shorter than the first period.

8. The semiconductor memory device of claim 6 , wherein:
the main memory area includes a main memory unit and a plurality of main page buffer groups corresponding thereto; and
the plurality of main page buffer groups correspond to the main data lines, respectively, and output data read from the main memory unit to the main data lines in response to first column selection signals.

9. The semiconductor memory device of claim 8 , wherein:
the redundancy memory area includes a redundancy memory unit and a redundancy page buffer group corresponding thereto;
the redundancy page buffer group is coupled to the redundancy data line and outputs data read from the redundancy memory unit to the redundancy data line in response to second column selection signals; and
the first column selection signals have the first period, and the second column selection signals have the second period.

10. The semiconductor memory device of claim 6 , wherein the sense amplifier circuit comprises:
a plurality of first sense amplifiers coupled to the main data lines, respectively; and
a second sense amplifier coupled to the redundancy data line,
wherein the plurality of first sense amplifiers perform sensing operations in parallel to sense potentials of the main data lines in response to the first strobe signals, respectively.

11. The semiconductor memory device of claim 10 , wherein each period of the sensing operations of the first sense amplifiers is shorter than a period of a sensing operation of the second sense amplifier.

12. A semiconductor memory device, comprising:
a memory cell part including a main memory unit and a redundancy memory unit;
a page buffer circuit including a plurality of page buffer groups and suitable for reading data stored in the memory cell part to temporarily store read data; and
a sensing circuit including a plurality of sense amplifiers corresponding to the plurality of page buffer groups, respectively, and suitable for sensing the read data in response to strobe signals,
wherein the plurality of sense amplifiers perform data sensing operations in parallel in order to sense the read data.

13. The semiconductor memory device of claim 12 , wherein:
the page buffer groups output the read data to a plurality of data lines in response to column selection signals, respectively; and
the sense amplifiers sense the read data outputted to the plurality of data lines in response to the strobe signals, respectively.

14. The semiconductor memory device of claim 13 , further comprising:
a column selection signal and strobe signal generation unit suitable for generating the column selection signals and the strobe signals.

15. The semiconductor memory device of claim 14 , wherein the column selection signal and strobe signal generation unit sequentially generates the column selection signals for each page buffer group, or alternately generates the column selection signals for the respective page buffer groups.

16. The semiconductor memory device of claim 14 , wherein the column selection signal and strobe signal generation unit sequentially generates the strobe signals for each sense amplifier, or alternately generates the strobe signals for the respective sense amplifiers.

17. The semiconductor memory device of claim 16 , wherein;
when the column selection signal and strobe signal generation unit sequentially generates the strobe signals, each of the strobe signals continuously toggles for an amount of data that is continuously transferred to a corresponding data line; and
when the column selection signal and strobe signal generation unit alternately generates the strobe signals, the strobe signals applied to the respective sense amplifiers alternately toggle once.

18. The semiconductor memory device of claim 13 , wherein:
the page buffer groups include a redundancy page buffer group corresponding to the redundancy memory unit; and
the sense amplifiers include a redundancy sense amplifier coupled to the redundancy page buffer group through one of the data lines.

19. The semiconductor memory device of claim 18 , wherein:
the page buffer groups include main page buffer groups corresponding to the main memory unit and the sense amplifiers include main sense amplifiers coupled to the main page buffer groups;
column selection signals applied to the main page buffer groups have a first period, and column selection signals applied to the redundancy page buffer group have a second period; and
strobe signals applied to the main sense amplifiers have the first period, and a strobe signal applied to the redundancy sense amplifier has the second period.

20. The semiconductor memory device of claim 19 , wherein the second per

Assignees

• Sk Hynix Inc

Inventors

• Lim Sang Oh

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title