Refresh of nonvolatile memory cells and reference cells with resistance drift

Patent metadata

Field	Value
Publication number	US-9472274-B1
Application number	US-201514788969-A
Country	US
Kind code	B1
Filing date	Jul 1, 2015
Priority date	Jul 1, 2015
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Resistance drift can be addressed by refreshing the nonvolatile memory cells and reference cells. Different approaches include performing the refresh upon a program operation, and upon satisfaction of a condition after the program operation. Refreshes are performed on a reference resistance stored in a reference cell that can be compared by a sense amplifier to the resistance stored in a memory cell. In one approach, upon programming the first memory cell, a stored refresh status is updated to indicate that the first resistance of the first memory cell and the first reference resistance of the first reference cell are to be refreshed upon satisfaction of a condition. In another approach, upon programming the first memory cell, the first reference cell is programmed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first memory cell having a first resistance;
sense amplifier circuitry including a first reference cell having a first reference resistance;
a memory storing a refresh status of the first reference cell, the refresh status including a first state and a second state; and
control circuitry that executes a refresh operation upon satisfaction of a condition, the refresh operation including refreshing the first reference cell and the first memory cell if the refresh status of the first reference cell is the first state, and not refreshing the first reference cell and the first memory cell if the refresh status is the second state, and that upon programming the first memory cell, updates the refresh status stored in the memory to the first state.

2. The integrated circuit of claim 1 , the control circuitry including logic that, if the first memory cell and the first reference cell are refreshed in the refresh operation, updates the refresh status of the first reference cell stored in the memory to the second state.

3. The integrated circuit of claim 1 , wherein the condition is passage of a time period.

4. The integrated circuit of claim 1 , wherein the condition is receipt by the control circuitry of a signal caused by an upcoming power off of the integrated circuit.

5. The integrated circuit of claim 1 , wherein the condition is receipt by the control circuitry of a signal caused by a backup power supply providing power to the integrated circuit.

6. The integrated circuit of claim 1 , wherein the first memory cell and the first reference cell share a same cell structure.

7. The integrated circuit of claim 1 , wherein the first memory cell and the first reference cell comprise programmable resistance material.

8. The integrated circuit of claim 1 , wherein the first resistance represents multiple bits, the first reference cell is one of a plurality of reference cells storing different reference resistances, the sense amplifier circuitry compares the first resistance to the different reference resistances to determine the multiple bits represented by the first resistance, and the plurality of reference cells are to be refreshed upon satisfaction of the condition.

9. The integrated circuit of claim 1 , wherein (i) the first memory cell having the first resistance, and (ii) the memory storing a refresh status of the first reference cell, are in separate arrays.

10. The integrated circuit of claim 1 , wherein the first memory cell and the first reference cell share a same memory array.

11. The integrated circuit of claim 1 , comprising a plurality of memory cell groups, and wherein the first memory cell is in one of the groups and the first reference cell and sense amplifier are coupled by decoding circuits to said one of the groups.

12. The integrated circuit of claim 1 , wherein:
the first resistance represents multiple bits;
the first reference cell is one of a plurality of reference cells representing different reference resistances;
the sense amplifier circuitry compares the first resistance to the different reference resistances to determine the multiple bits represented by the first resistance; and
the control circuitry programs the first memory cell upon receiving a program instruction of the first memory cell.

13. An integrated circuit, comprising:
an array of memory cells including a plurality of groups of memory cells having resistances;
a plurality of sense amplifiers including a plurality of sets of reference cells having reference resistances, sets of reference cells in the plurality of sets of reference cells corresponding to different groups of memory cells in the plurality of groups of memory cells via sense amplifiers in the plurality of sense amplifiers;
a memory storing refresh statuses of the plurality of groups of memory cells, the refresh status of a group in the plurality of groups including a first state and a second state; and
control circuitry that executes a refresh operation upon satisfaction of a condition, the refresh operation including refreshing at least one memory cell in a particular group of memory cells and the set of reference cells corresponding to the particular group if the refresh status of the particular group is the first state, and not refreshing the particular group of memory cells and its corresponding set of reference cells if the refresh status of the particular group is the second state, and that, upon programming one or more memory cells in a first group of memory cells in the plurality of groups of memory cells, updates the refresh status of the first group stored in the memory to the first state.

14. The integrated circuit of claim 13 , wherein the control circuitry including logic that, for groups of memory cells and corresponding sets of reference cells that are refreshed in the refresh operation, updates the refresh statuses stored in the memory of the refreshed groups of memory cells to the second state.

Assignees

• Macronix Int Co Ltd

Inventors

• Lung Hsiang-Lan

Classifications

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title