TFT-LCD array substrate pixel electrode connected to first and second capacitors

Patent metadata

Field	Value
Publication number	US-9470946-B2
Application number	US-201314066630-A
Country	US
Kind code	B2
Filing date	Oct 29, 2013
Priority date	Jul 25, 2012
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A pixel unit at a TFT-LCD array substrate includes a thin film transistor, a first storage capacitor, and a second storage capacitor. The first storage capacitor includes a transparent common electrode, a pixel electrode, and a first insulating layer disposed between the transparent common electrode and the pixel electrode. The second storage capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer disposed between the first and second conductive layers. The first conductive layer is connected to the transparent common electrode within the pixel unit. The second conductive layer is connected to the pixel electrode within the pixel unit.

First claim

What is claimed is:

1. A pixel unit of an IPS type TFT-LCD array substrate having a plurality of pixel units, the pixel unit comprising:
a thin film transistor switch, a pixel electrode, and a transparent common electrode, so that a parallel electric field is formed between the pixel electrode and the transparent common electrode; wherein the transparent common electrode is located between the pixel electrode and a substrate;
a first storage capacitor being formed by the transparent common electrode, the pixel electrode, and a first insulating layer disposed between the transparent common electrode and the pixel electrode; and
a second storage capacitor being formed by a first conductive layer, a second conductive layer, and a second insulating layer disposed between the first conductive layer and the second conductive layer;
wherein the first conductive layer is electrically connected within the pixel unit to the transparent common electrode and the second conductive layer is electrically connected within the pixel unit to the pixel electrode, so that a common electrode potential is provided to the first conductive layer or the second conductive layer by the transparent common electrode connected thereto; wherein the first conductive layer and the transparent common electrode are formed in different layers, and wherein the second conductive layer and the pixel electrode are formed in different layers.

2. The pixel unit of claim 1 , further comprising in sequence from bottom to top:
a polysilicon layer including a channel, a source electrode, and a drain electrode;
a gate insulating layer;
a gate electrode;
a passivation layer;
a data line, a source electrode metal structure, and a drain electrode metal structure on the passivation layer, the source electrode metal structure, the drain electrode metal structure;
an organic film layer;
the transparent common electrode;
the first insulating layer; and
the pixel electrode.

3. The pixel unit of claim 2 , wherein
the first conductive layer is in the same layer with the gate electrode, and is connected with the transparent common electrode through a contact hole;
the second conductive layer is in the same layer with the drain electrode at the polysilicon layer, and is connected with the drain electrode; and
the second insulating layer is the gate insulating layer.

4. The pixel unit of claim 3 , wherein
the first conductive layer and the gate electrode are formed in the same process step; and
the second conductive layer and the drain electrode at the polysilicon layer are formed in the same process step.

5. The pixel unit of claim 2 , wherein
the first conductive layer is in the same layer with the gate electrode, and is connected with the transparent common electrode through a metal conductive pad;
the second conductive layer is in the same layer with the drain electrode at the polysilicon layer, and is connected with the drain electrode; and
the second insulating layer is the gate insulating layer.

6. The pixel unit of claim 5 , wherein
the metal conductive pad, the data line, the source electrode metal structure, and the drain electrode metal structure are formed in the same layer and formed in the same process step, the metal conductive pad having one side connected with the first conductive layer through a first contact hole, and an opposite side connected with the transparent common electrode through a second contact hole.

7. The pixel unit of claim 2 , wherein
the first conductive layer is in the same layer with the drain electrode metal structure, and is connected with the transparent common electrode through a contact hole;
the second conductive layer is in the same layer with the gate electrode, and is connected with the drain electrode metal structure through a contact hole; and
the second insulating layer is the passivation layer.

8. The pixel unit of claim 7 , wherein
the first conductive layer and the drain electrode metal are formed in the same process step; and
the second conductive layer and the gate electrode are formed in the same process step.

9. The pixel unit of claim 1 , further comprising:
a gate electrode on the substrate;
a gate insulating layer on the gate electrode;
a polysilicon layer on the gate insulating layer, the polysilicon layer including a channel, a source electrode and a drain electrode;
a passivation layer on the polysilicon layer;
a data line, a source electrode metal structure and a drain electrode metal structure on the passivation layer;
an organic film layer on the data line, the source electrode metal structure and on the drain electrode metal structure;
the transparent common electrode on the organic film layer;
the first insulating layer on the transparent common electrode; and
the pixel electrode on the first insulating layer.

10. The pixel unit of claim 9 , wherein
the first conductive layer is in the same layer with the gate electrode, and is connected with the transparent common electrode through a contact hole;
the second conductive layer and the drain electrode are formed on a same second layer, the second conductive layer connected with the drain electrode; and
the second insulating layer is the gate insulating layer.

11. The pixel unit of claim 10 , wherein
the first conductive layer and the gate electrode are formed in the same process step; and
the second conductive layer and the drain electrode are formed in the same process step.

12. The pixel unit of claim 9 , wherein
the first conductive layer and the gate electrode are formed in a same layer, the first conductive layer connected with the transparent common electrode through a metal conductive pad;
the second conductive layer and the drain electrode are formed in a same layer, the second conductive layer connected with the drain electrode; and
the second insulating layer is the gate insulating layer.

13. A method for manufacturing an IPS type TFT-LCD array containing a plurality of pixel units, the method comprising:
providing a substrate including the TFT-LCD array, each of the pixel units having an area, wherein a pixel unit comprises:
a thin film transistor switch, a pixel electrode, a transparent common electrode, and a first insulating layer disposed between the transparent common electrode and the pixel electrode, so that a parallel electric field is formed between the pixel electrode and the transparent common electrode; wherein the transparent common electrode is located between the pixel electrode and a substrate;
a first storage capacitor being formed by the transparent common electrode, the pixel electrode, and the first insulating layer; and
a second storage capacitor being formed by a first conductive layer, a second conductive layer, and a second insulating layer disposed between the first conductive layer and the second conductive layer;
wherein the first conductive layer is electrically connected within the area of the pixel unit to the transparent common electrode and the second conductive layer is electrically connected within the area of the pixel unit to the potential of the transparent common electrode and that of the pixel electrode, so that a common electrode potential is provided to the first conductive layer or the second conductive layer by the transparent common electrode connected thereto; the first conductive layer and the transparent common electrode are formed in different layers, the second conductive layer and the pixel electrode are formed in different layers.

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Shanghai Tianma Micro-Electroincs Co Ltd

Inventors

• Gu Hanyu
• Qian Dong
• Tseng Chang-Ho

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2201/40

  Arrangements for improving the aperture ratio · CPC title

• G02F1/136213 Primary

  Storage capacitors associated with the pixel electrode · CPC title