Measuring power consumption of circuit component operating in ultra-low power mode

US9470725B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9470725-B2
Application numberUS-201313953530-A
CountryUS
Kind codeB2
Filing dateJul 29, 2013
Priority dateJul 29, 2013
Publication dateOct 18, 2016
Grant dateOct 18, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacitance using a mathematical formula.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of obtaining measurement data for a circuit component, the method comprising: charging a capacitor to a voltage level using a power system of the circuit component; disconnecting, by a control logic that is distinct from the circuit component, the power system of the circuit component, and enabling the capacitor to discharge and to power the circuit component; responsive to the enabling, starting a counter; stopping the counter when the capacitor has discharged to a trip voltage; and obtaining measurement data for the circuit component, comprising obtaining, using a value measured by the counter, a discharge time of the capacitor. 2. The method of claim 1 , where the trip voltage is calculated from a product of the voltage level and a fixed constant. 3. The method of claim 1 , further comprising: comparing a voltage across the capacitor with the trip voltage; and generating a trip signal when the voltage across the capacitor is less than or equal to the trip voltage. 4. The method of claim 1 , further comprising: determining that the circuit component has transitioned out of an ultra-low power mode; and reconnecting the capacitor to the power system. 5. The method of claim 1 , where the circuit component is a microcontroller. 6. The method of claim 1 , further comprising: storing measurement data for a discharge period; and enabling access to the measurement data by another component or application. 7. The method of claim 1 , wherein the value measured by the counter includes a time period for which the capacitor is discharged. 8. The method of claim 1 , further comprising: prior to charging the capacitor, applying a known current to the capacitor for a period of time using a current sink; determining a calibration factor using the known current and the period of time; and obtaining the measurement data for the circuit component using the value measured by the counter and the calibration factor. 9. The method of claim 8 , where the calibration factor is given by CΔV=ΔI*Δt where C is the capacitance of the capacitor, ΔV is the voltage across the capacitor, ΔI is the known current and Δt is the time period. 10. A circuit for obtaining measurement data from a circuit component, comprising: a capacitor coupled to a power system of the circuit component; control logic distinct from the circuit component and configured to disconnect the power system of the circuit component to enable the capacitor to discharge and to power the circuit component; and a counter coupled to the control logic and configured to determine a discharge period. 11. The circuit of claim 10 , where the circuit component is a microcontroller. 12. The circuit of claim 10 , further comprising: a comparator having inputs coupled to the capacitor and a trip voltage and an output coupled to the control logic, the comparator configured to compare a voltage across the capacitor and the trip voltage and to generate a trip signal based on the comparing. 13. The circuit of claim 12 , further comprising: a clock coupled to the control logic and the counter, the clock configured to start and stop the counter using a clock gate signal generated by the control logic. 14. The circuit of claim 12 , further comprising: a switch configured to selectively couple the power system to the capacitor; and a first latch having an input coupled to the output of the comparator and an output coupled to the switch, the first latch configured to selectively open and close the switch in response to the trip signal. 15. The circuit of claim 14 , further comprising: a second latch configured for latching the output of the counter. 16. The circuit of claim 12 , further comprising: a current sink configured to apply a known current to the capacitor for a period of time to allow a calibration factor to be obtained. 17. The circuit of claim 16 , where the calibration factor is given by CΔV=ΔI*Δt where C is the capacitance of the capacitor, ΔV is the voltage across the capacitor, ΔI is the known current and Δt is the time period.

Assignees

Inventors

Classifications

  • Current or voltage test · CPC title

  • Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

  • G01R21/006Primary

    Measuring power factor · CPC title

  • Measuring quality factor or dielectric loss, e.g. loss angle, or power factor (power factor related to power measurements G01R21/006; testing capacitors G01R31/016) · CPC title

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What does patent US9470725B2 cover?
By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacita…
Who is the assignee on this patent?
Atmel Corp
What technology area does this patent fall under?
Primary CPC classification G01R31/3004. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 18 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).