System for generation of a synchronization signal via stations connected via a packet switching network

Patent metadata

Field	Value
Publication number	US-9467722-B2
Application number	US-46099609-A
Country	US
Kind code	B2
Filing date	Jul 28, 2009
Priority date	Jul 29, 2008
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. It relates more specifically to a system for generation of a synchronization signal (PIPA, PIPB) and a clock signal (CLK_outA, CLK_outB) by a slave station (SA, SB) connected to a master station (SM) via a packet switching network. The master station (SM) is conformed to produce a master clock signal (CLKM) of frequency F M and a master synchronization signal (PIPM). The master synchronization signal (PIPM) is in phase with the master clock signal (SM). The slave station (SA, SB) comprises the primary synthesis means (SM 1 A, SM 1 B) producing a slave periodic signal TICKSA, TICKSB), the periodic signal (TICKSA, TICKSB) is in phase with the master clock signal (CLKM). According to the invention, the slave station (SA, SB) also comprises the secondary means of synthesis (SM 2 A, SM 2 B) to synthesize a clock signal (CLK_outA, CLK_outB) and the synchronization signal (PIPA, PIPB) and in that said clock signal (CLK_outA, CLK_outB) and said synchronization signal (PIPA, PIPB) are in phase with said signal (TICKSA, TICKSB).

First claim

The invention claimed is:

1. A slave station apparatus comprising:
a phase-locked loop comprising a filter, a configurable oscillator; and a first stage frequency divider;
a second stage frequency divider;
a counter; and
circuitry configured to:
detect a master clock signal of frequency F M and a master synchronization signal received from a packet switching network, wherein said master synchronization signal is in phase with the master clock signal;
produce, using the second stage frequency divider, a slave periodic signal, wherein said slave periodic signal is in phase with the master clock signal and the slave periodic signal is of frequency F M /p where p is an integer;
generate a slave clock signal identical to the master clock signal;
detect the slave clock signal produced by the second stage frequency divider; detect, using the phase-locked loop, the slave periodic signal;
generate, using the configurable oscillator, a clock signal having a frequency F that is in phase with the slave periodic signal
detect, using the first stage frequency divider, the clock signal having the frequency F that is in phase with the slave periodic signal;
produce, using the first stage frequency divider, a local periodic signal of frequency F/q where q is an integer;
detect, using the counter, the clock signal having the frequency F that is in phase with the slave periodic signal;
send, via a decoder, a video synchronization signal;
initialize, using the counter, the video synchronization signal based at least partially on a first stage initialization signal in phase with the slave periodic signal;
compare the local periodic signal and the slave periodic signal using the phase locked loop so as to produce a comparison result;
detect the comparison result with the filter; and
generate, using the filter, a filtered result and send the filtered result to the configurable oscillator, the first stage initialization signal being the local periodic signal.

2. The slave station apparatus according to claim 1 , wherein said second stage divider is initialized by a stage initialization signal.

3. The slave station apparatus according to claim 2 , wherein the circuitry is configured to generate the slave clock signal based at least partially on a value of a first counter and a value of a second counter from which the slave periodic signal and the slave clock signal are based, the value of the first counter and the value of the second counter being received from the network.

4. The slave station apparatus according to claim 3 , wherein the master synchronization signal and the slave periodic signal are produced from the value of the first counter.

5. The slave station apparatus according to claim 3 , wherein the master clock signal and the slave clock signal are produced from the value of the second counter.

6. The slave station apparatus according to claim 1 , wherein the video synchronization signal is a Genlock signal.

7. A method comprising:
detecting a master clock signal of frequency F M and a master synchronization signal received from a packet switching network, wherein said master synchronization signal is in phase with the master clock signal;
producing, using a second stage frequency divider, a slave periodic signal, wherein said slave periodic signal is in phase with the master clock signal and the slave periodic signal is of frequency F M /p where p is an integer;
generating a slave clock signal identical to the master clock signal;
detecting the slave clock signal produced by the second stage frequency divider;
detecting, using a phase-locked loop, the slave periodic signal;
generating, using a configurable oscillator in the phase-locked loop a clock signal having a frequency F that is in phase with the slave periodic signal;
detecting, using a first stage frequency divider, the clock signal having the frequency F that is in phase with the slave periodic signal;
producing, using the first stage frequency divider, a local periodic signal of frequency F/q where q is an integer;
detecting, using a counter, the clock signal having the frequency F that is in phase with the slave periodic signal;
send, via a decoder, a video synchronization signal;
initializing, using the counter, the video synchronization signal based at least partially on a first stage initialization signal in phase with the slave periodic signal;
comparing the local periodic signal and the slave periodic signal using the phase locked loop so as to produce a comparison result;
detecting the comparison result with a filter of the phase-locked loop;
generating, using the filter, a filtered result; and
sending, by the filter, the filtered result to the configurable oscillator, the first stage initialization signal being the local periodic signal.

8. The method according to claim 7 , further comprising initializing the second stage frequency divider with a stage initialization signal.

9. The method according to claim 8 , further comprising:
generating the slave clock signal based at least partially on a value of a first counter and a value of a second counter from which the slave periodic signal and the slave clock signal are based, the value of the first counter and the value of the second counter being received from the network.

10. The method according to claim 9 , further comprising producing the master synchronization signal and the slave periodic signal from the value of the first counter.

11. The method according to claim 9 , further comprising producing the master clock signal and the slave clock signal from the value of the second counter.

12. The method according to claim 7 , wherein the video synchronization signal is a Genlock signal.

Assignees

• Tapie Thierry
• Defrance Serge
• Rio Philippe
• Thomson Licensing

Inventors

• Tapie Thierry
• Defrance Serge
• Rio Philippe

Classifications

• H04N21/4341

  Demultiplexing of audio and video streams · CPC title

• H04N21/2368

  Multiplexing of audio and video streams · CPC title

• H04N21/242 Primary

  Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)} · CPC title

• H04J3/0664

  unidirectional timestamps · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title