Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar

Patent metadata

Field	Value
Publication number	US-9467396-B2
Application number	US-201414250702-A
Country	US
Kind code	B2
Filing date	Apr 11, 2014
Priority date	Apr 11, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A method for scheduling a crossbar using distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a switch unit is provided. The switch unit may be a hierarchical high radix switch with a timesliced crossbar that is configured to transfer packets between a plurality of input ports and a plurality of output ports, organized into groups, using wide words. The timesliced crossbar transfers data for a given packet once per supercycle, in a designated timeslice of that supercycle. Multiple buffered packets from one input port to multiple output ports are transferred by utilizing different timeslices of the supercycle.

First claim

What is claimed is:

1. A computer program product for scheduling a crossbar using distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a switch unit, the computer program product comprising:
a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising:
computer-readable program code configured to select a first input port of an input group according to a first arbitration operation, wherein the input group comprises a plurality of input ports including the first input port having buffered packets targeting a plurality of output ports;
computer-readable program code configured to, transfer, by operation of a crossbar, a first packet of the buffered packets from the first input port during a first timeslice of a cycle, wherein the cycle comprises a plurality of timeslices;
computer-readable program code configured to select the first input port according to a second arbitration operation, further comprising computer-readable program code configured to generate a request for the input group that includes availability of the first input port, while the first input port is transferring the first packet during the first timeslice of the cycle; and
computer-readable program code configured to, transfer, by operation of the crossbar, a second packet of the buffered packets from the same first input port during a second timeslice of the cycle.

2. The computer program product of claim 1 , wherein the first arbitration operation comprises a request-grant-accept arbitration between an input arbiter associated with the input group and an output arbiter associated with the plurality of output ports.

3. The computer program product of claim 1 , wherein the crossbar has a data width that is greater than an incoming data rate of the first input port.

4. The computer program product of claim 1 , wherein the number of timeslices in a cycle is determined based on a ratio of a data width of the crossbar to an incoming data rate of the first input port.

5. The computer program product of claim 1 , wherein the first packet is transferred to a first output port of an output group, and the second packet is transferred to a second output port.

6. The computer program product of claim 1 , wherein the first packet is transferred to a first output port of an output group, and the second packet is transferred to the same first output port.

7. An apparatus comprising:
a plurality of input ports including a first input port organized into input groups;
a plurality of output ports organized into output groups;
a crossbar configured to selectively connect the plurality of input ports to the plurality of output ports;
a computer processor; and
a memory storing firmware, which, when executed on the computer processor, performs an operation comprising:
selecting the first input port of an input group according to a first arbitration operation, the first input port having buffered packets targeting at least one of the plurality of output ports;
transferring, by operation of the crossbar, a first packet of the buffered packets from the first input port during a first timeslice of a cycle, wherein the cycle comprises a plurality of timeslices;
selecting the first input port according to a second arbitration operation, wherein selecting the first input port comprises generating a request for the input group that includes availability of the first input port, while the first input port is transferring the first packet during the first timeslice of the cycle; and
transferring, by operation of the crossbar, a second packet of the buffered packets from the same first input port during a second timeslice of the cycle.

8. The apparatus of claim 7 , wherein the first arbitration operation comprises a request-grant-accept arbitration between an input arbiter associated with the input group and an output arbiter associated with the plurality of output ports.

9. The apparatus of claim 7 , wherein the crossbar has a data width that is greater than an incoming data rate of the first input port.

10. The apparatus of claim 7 , wherein the number of timeslices in a cycle is determined based on a ratio of a data width of the crossbar to an incoming data rate of the first input port.

11. The apparatus of claim 7 , wherein the first packet is transferred to a first output port of an output group, and the second packet is transferred to a second output port.

12. The apparatus of claim 7 , wherein the first packet is transferred to a first output port of an output group, and the second packet is transferred to the same first output port.

Assignees

• IBM

Inventors

• Chrysos Nikolaos
• Gopala Kurup Girish
• Minkenberg Cyriel J
• Pothireddy Anil
• Srivastava Vibhor K
• Vanderpool Brian T

Classifications

• H04L49/90

  Buffering arrangements · CPC title

• H04L49/254

  Centralised controller, i.e. arbitration or scheduling · CPC title

• H04L49/1523

  Parallel switch fabric planes · CPC title

• H04L49/101 Primary

  using crossbar or matrix · CPC title