Handling large frames in a virtualized fibre channel over ethernet (FCoE) data forwarder

US9467389B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9467389-B2
Application numberUS-201414263015-A
CountryUS
Kind codeB2
Filing dateApr 28, 2014
Priority dateApr 28, 2014
Publication dateOct 11, 2016
Grant dateOct 11, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A switch unit has one frame buffer pool for storing received frames and another frame buffer pool for storing large frames. The frame size in the large frame buffer pool may be optimized to the largest amount of data the switch unit that an FCoE switching is running on can support (i.e., a limitation of zone entries). Should free space be unavailable in the large frame buffer pool, or if a sequence grows bigger than can be supported, the switch unit may still continue to send response frames back to the sender. While the switch unit may store header information of the frame, the switch unit does not store the data of subsequent frames any longer. Once the sequence has been received completely, a rejection message is sent back with an appropriate error or reason code. The rejection message enables the sender to attempt a retransmission or cancel the current request altogether.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer program product for managing a distributed Fibre Channel fabric, the computer program product comprising: a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising: computer-readable program code configured to receive a frame at a Fibre Channel (FC) interface of a switch unit; computer-readable program code configured to determine whether the received frame is part of a multi-frame sequence; computer-readable program code configured to, responsive to determining the received frame is not part of a multi-frame sequence, store the received frame in a first frame buffer pool, wherein the first frame buffer pool comprises a first plurality of memory blocks sized with a maximum size of an individual FC frame; and computer-readable program code configured to, responsive to determining the received frame is part of a multi-frame, store the received frame in a second frame buffer pool, wherein the second frame buffer pool comprises a second plurality of memory blocks sized based on hardware zoning capabilities of the switch unit, and wherein the computer-readable program code configured to store the received frame in the second frame buffer pool comprises: computer-readable program code configured to, responsive to determining that the multi-frame sequence associated with the received frame would have exceeded the hardware zoning capabilities of the switch unit, set an error flag indicating that the multi-frame sequence exceeds the hardware zoning capabilities of the switch unit, and computer-readable program code configured to, responsive to receiving a last frame of the multi-frame sequence and if the error flag is set, transmit a rejection sequence notifying a sender of the frame of the error flag, wherein the rejection sequence indicates the sender should not attempt retransmission of the frame. 2. The computer program product of claim 1 , wherein the computer-readable program code configured to store the received frame in the second frame buffer pool further comprises: computer-readable program code configured to, responsive to determining that the received frame is a first frame of the multi-frame sequence, register header information of the received frame as exchange data; computer-readable program code configured to allocate a memory block from the second frame buffer pool; and computer-readable program code configured to copy the received frame to the memory block of the second frame buffer pool. 3. The computer program product of claim 1 , further comprising computer-readable program code configured to transmit, to the sender of the frame, a response frame that acknowledges receipt of the frame, wherein the response frame causes an increase of end-to-end credit at the sender of the frame. 4. The computer program product of claim 1 , further comprising: computer-readable program code configured to transmit to the sender of the frame a response frame acknowledging receipt of the frame, wherein the frame is discarded by the switch unit. 5. The computer program product of claim 1 , wherein the multi-frame sequence of the received frame comprises at least one of a N_Port _ID and Zoning ACL Distribution (NPZD) request sequence and an Active Zoning ACL Distribution (AZAD) request sequence. 6. An apparatus, comprising: a memory comprising a first frame buffer pool and a second frame buffer pool, wherein the first frame buffer pool comprises a first plurality of memory blocks sized with a maximum size of an individual Fibre Channel (FC) frame, and wherein the second frame buffer pool comprises a second plurality of memory blocks sized based on hardware zoning capabilities of the apparatus; and one or more computer processors configured to perform an operation comprising: receiving a frame at a FC interface of the apparatus; determining, by operation of the one or more computer processors, whether the received frame is part of a multi-frame sequence; responsive to determining the received frame is not part of a multi-frame sequence, storing the received frame in the first frame buffer pool; and responsive to determining the received frame is part of a multi-frame, storing the received frame in a second frame buffer pool, wherein the one or more computer processors configured to store the received frame in the second frame buffer pool are further configured to perform the operation comprising: responsive to determining that the multi-frame sequence associated with the received frame would have exceeded the hardware zoning capabilities of the apparatus, setting an error flag indicating that the multi-frame sequence exceeds the hardware zoning capabilities of apparatus; and responsive to receiving a last frame of the multi-frame sequence and if the error flag is set, transmitting a rejection sequence notifying a sender of the frame of the error flag, wherein the rejection sequence indicates the sender should not attempt retransmission of the frame. 7. The apparatus of claim 6 , wherein the one or more computer processors configured to store the received frame in the second frame buffer pool are further configured to perform the operation comprising: responsive to determining that the received frame is a first frame of the multi-frame sequence, registering header information of the received frame as exchange data; allocating a memory block from the second frame buffer pool; and copying the received frame to the memory block of the second frame buffer pool. 8. The apparatus of claim 6 , wherein the one or more computer processors are further configured to perform the operation comprising: transmitting, to the sender of the frame, a response frame that acknowledges receipt of the frame, wherein the response frame causes an increase of end-to-end credit at the sender of the frame. 9. The apparatus of claim 6 , wherein the one or more computer processors are further configured to perform the operation comprising: transmitting to the sender of the frame a response frame acknowledging receipt of the frame, wherein the frame is discarded by the apparatus. 10. The apparatus of claim 6 , wherein the first plurality of memory blocks of the first frame buffer pool comprise 2148-byte memory blocks, and wherein the second plurality of memory blocks of the second frame buffer pool have a larger size than the first plurality of memory blocks. 11. The apparatus of claim 6 , wherein the multi-frame sequence of the received frame comprises at least one of a N_Port _ID and Zoning ACL Distribution (NPZD) request sequence and an Active Zoning ACL Distribution (AZAD) request sequence.

Assignees

Inventors

Classifications

  • H04L47/62Primary

    characterised by scheduling criteria · CPC title

  • LAN interconnection over a bridge based backbone · CPC title

  • Single bridge functionality, e.g. connection of two networks over a single bridge · CPC title

  • for local area network [LAN], e.g. Ethernet switches · CPC title

  • Reactions to storage capacity overflow · CPC title

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Frequently asked questions

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What does patent US9467389B2 cover?
A switch unit has one frame buffer pool for storing received frames and another frame buffer pool for storing large frames. The frame size in the large frame buffer pool may be optimized to the largest amount of data the switch unit that an FCoE switching is running on can support (i.e., a limitation of zone entries). Should free space be unavailable in the large frame buffer pool, or if a sequ…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H04L47/62. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).