Systems, circuits and methods related to multi-mode power amplifiers having improved linearity

Patent metadata

Field	Value
Publication number	US-9467101-B2
Application number	US-201414531966-A
Country	US
Kind code	B2
Filing date	Nov 3, 2014
Priority date	Nov 7, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Multi-mode power amplifiers (PAs) having improved linearity. A PA can include an amplifying bipolar junction transistor (BJT) configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a biasing circuit configured to provide a first bias signal or a second bias signal to the BJT for operation in a first mode or a second mode. Each of the first bias signal and the second bias signal can be routed to the BJT through a path that includes a common node and a ballast. The PA can further include a linearizing circuit implemented between the common node and a node along an input path for the BJT. The linearizing circuit can be configured as a coupling path to improve linearity of the PA operating in the first mode while allowing the ballast to be sufficiently robust for the PA operating in the second mode.

First claim

What is claimed is:

1. A power-amplifier (PA) comprising:
a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal, the input path including a capacitance implemented between an input node and the base of the BJT;
a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the base of the BJT for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and
a linearizing circuit implemented between the common node and the input node of the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in at least one of the first mode and the second mode.

2. The PA of claim 1 wherein the ballast includes a DC ballasting resistance.

3. The PA of claim 1 wherein the BJT includes a heterojunction bipolar transistor (HBT).

4. The PA of claim 1 wherein the linearizing circuit providing the coupling path between the common node and the input path improves linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode.

5. A power-amplifier (PA) comprising:
a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal at the base through an input path and amplify the RF signal, the amplified RF signal being output through the collector;
a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and
a linearizing circuit implemented between the common node and a node along the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode, the first mode including an EDGE (enhanced data rates for GSM evolution) mode, and the second mode including a GPRS (general packet radio service) mode.

6. The PA of claim 5 wherein the biasing circuit includes a current mirror that generates the first bias signal for the operation of the PA circuit in the EDGE mode.

7. The PA of claim 6 wherein the current mirror includes a BJT coupled to a reference current source, the first bias signal being output through an emitter of the BJT to be provided to the common node.

8. The PA of claim 7 wherein the ballast is implemented between the common node and the base of the PA BJT, such that the common node functions as a base-emitter junction between the base of the PA BJT and the emitter of the current mirror BJT.

9. The PA of claim 8 wherein the input path includes a DC blocking capacitance implemented between the base of the PA BJT and a node where the linearizing circuit is connected to.

10. The PA of claim 9 wherein the linearizing circuit is configured to couple the RF signal between the input path and the base-emitter junction to provide rectification on the base-emitter junction and correct AM-AM distortion and thereby yield the improved linearity.

11. The PA of claim 5 wherein the biasing circuit includes a bias resistance implemented between a GPRS bias node and the common node, such that the second bias signal is provided to the gate of the BJT from the GPRS bias node through the bias resistance, the common node, and the ballast.

12. The PA of claim 1 wherein the PA circuit includes a second BJT configured to provide another stage of amplification.

13. The PA of claim 12 wherein the second BJT is implemented so that the input path of the BJT is coupled to an output of the second BJT.

14. The PA of claim 12 wherein the BJT is configured to receive the RF signal from the second BJT.

15. The PA of claim 1 wherein the linearizing circuit includes a capacitance.

16. The PA of claim 1 wherein the capacitance of the input path is configured as a DC block capacitance.

17. A power-amplifier (PA) comprising:
a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal;
a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and
a linearizing circuit implemented between the common node and a node along the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode, the linearizing circuit including a series arrangement of a capacitance and a resistance.

18. A power-amplifier (PA) comprising:
a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal;
a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and
a linearizing circuit implemented between the common node and a node along the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode, the linearizing circuit including a series arrangement of a capacitance and an inductance.

19. A power-amplifier (PA) module comprising:
a packaging substrate configured to receive a plurality of components;
a power amplifier (PA) circuit formed on a die that is mounted on the packaging substrate, the PA circuit including a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal, the input path including a capacitance implemented between an input node and the base of the BJT;
a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the base of the BJT for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a pat

Assignees

• Skyworks Solutions Inc

Inventors

• Ni Jianxing

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/231

  Arrangements for applying bias · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title