Grain growth for solar cells

US9466754B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9466754-B2
Application numberUS-201414447526-A
CountryUS
Kind codeB2
Filing dateJul 30, 2014
Priority dateJul 30, 2014
Publication dateOct 11, 2016
Grant dateOct 11, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A solar cell can include a silicon layer formed over a silicon substrate. The silicon layer can have a P-type doped region and an N-type doped region. Portions of the silicon layer can have a grain size larger than other portions of the silicon layer. For example, larger grains of the silicon layer formed within a depletion region between P-type and N-type doped regions can minimize recombination loss at the P-type and N-type doped region boundaries and improve solar cell efficiency.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a solar cell, the method comprising: forming upper regions, angled regions and lower regions of a silicon substrate, wherein the upper regions and the lower regions are substantially coplanar; forming a silicon layer over the silicon substrate; applying a laser to the silicon layer resulting in portions of the silicon layer over the upper regions and lower regions having a larger grain size than other portions of the silicon layer over angled regions of the silicon substrate; and driving dopants into the silicon layer resulting in P-type doped regions and N-type doped regions, the P-type doped regions and N-type doped regions abutting in a contiguous portion of the silicon layer. 2. The method of claim 1 , wherein forming upper regions, angled regions and lower regions comprises performing an etching process on the silicon substrate. 3. The method of claim 2 , wherein performing the etching process comprises etching with potassium hydroxide (KOH). 4. The method of claim 1 , further comprising forming a dielectric region between the silicon layer and the silicon substrate. 5. The method of claim 1 , wherein applying a laser comprises applying a pulsed laser or a continuous wave laser. 6. The method of claim 1 , wherein applying a laser comprises melting portions of the silicon layer. 7. The method of claim 1 , wherein applying a laser comprises applying a laser with a top-hat profile on the on the silicon layer. 8. The method of claim 1 , wherein forming a silicon layer comprises forming an amorphous silicon layer or a polysilicon layer. 9. A method of fabricating a solar cell, the method comprising: forming upper regions, angled regions and lower regions of a silicon substrate, wherein the upper regions and the lower regions are substantially coplanar; forming a silicon layer over the silicon substrate; and applying a laser to the silicon layer resulting in P-type doped regions and N-type doped regions and portions of the silicon layer over the upper regions and lower regions having a larger grain size than other portions of the silicon layer over angled regions of the silicon substrate, the larger grain size formed in a contiguous portion of the silicon layer where the P-type doped regions and N-type doped regions abut. 10. The method of claim 9 , wherein forming upper regions, angled regions and lower regions comprises performing an etching process on the silicon substrate. 11. The method of claim 10 , wherein performing the etching process comprises etching with potassium hydroxide (KOH). 12. The method of claim 9 , further comprising forming a dielectric between the silicon layer and the silicon substrate. 13. The method of claim 9 , wherein applying a laser comprises applying a pulsed laser or a continuous wave laser. 14. The method of claim 9 , wherein applying a laser comprises: driving dopants into the silicon layer using a laser resulting in P-type doped regions and N-type doped regions; and melting the portions of the silicon layer using the laser in a single step as the driving, the melting resulting in portions of the silicon layer over the upper regions and lower regions having a larger grain size than other portions of the silicon layer and the larger grain size formed in a contiguous portion of the silicon layer where the P-type doped regions and N-type doped regions abut. 15. The method of claim 9 , wherein applying a laser comprises applying a laser with a top-hat profile on the on the silicon layer. 16. The method of claim 9 , wherein forming a silicon layer comprises forming an amorphous silicon layer or a polysilicon layer.

Assignees

Inventors

Classifications

  • including only Group IV materials · CPC title

  • Shapes of bodies · CPC title

  • Recrystallisation; Crystallization of amorphous or microcrystalline semiconductors · CPC title

  • H10F71/128Primary

    Annealing · CPC title

  • The active layers comprising only Group IV materials · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9466754B2 cover?
A solar cell can include a silicon layer formed over a silicon substrate. The silicon layer can have a P-type doped region and an N-type doped region. Portions of the silicon layer can have a grain size larger than other portions of the silicon layer. For example, larger grains of the silicon layer formed within a depletion region between P-type and N-type doped regions can minimize recombinati…
Who is the assignee on this patent?
Kim Taeseok, Sunpower Corp
What technology area does this patent fall under?
Primary CPC classification H10F71/128. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).