Array substrate and fabrication method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9466624-B2
Application number	US-201414429961-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Oct 17, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Embodiments of the present disclosure provide an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate includes: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate. The forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film and a source-drain metal film on the base substrate; forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process. The number of the exposing process is reduced, the production cycle is shortened and the fabrication cost is reduced.

First claim

What is claimed is:

1. A fabrication method of an array substrate, comprising:
forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate, wherein the gate metal layer comprises at least a gate electrode and a metal pad;
wherein the forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises:
forming a gate insulating film, an active layer film, and a source-drain metal film on the base substrate; and
forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process,
wherein in a via hole is formed during the single pattern process, with the via hole penetrating the source-drain metal layer, the active layer and the gate insulating layer and reaching the metal pad.

2. The fabrication method according to claim 1 , wherein
the array substrate comprises a display pixel region, a connection region and an isolation region, the display pixel region is configured for displaying an image, the connection region is provided with the via hole, the via hole is configured for implementing an electrical connection between the metal pad and a external drive circuit, and the isolation region is configured for disconnecting a portion of the source-drain metal layer in the display pixel region from a portion of the source-drain metal layer in the connection region; and
the source-drain metal layer at least comprises a source electrode and a drain electrode, and the active layer comprises an active layer pattern.

3. The fabrication method according to claim 2 , wherein
the forming the gate insulating layer, the active layer and the source-drain metal layer by the single patterning process comprises the steps of:
coating a photoresist on the base substrate provided with the gate insulating film, the active layer film, and the source-drain metal film;
exposing and developing the base substrate provided with photoresist by using a multi-tone mask to forma first photoresist-reserved-portion, a second photoresist-reserved-portion, a third photoresist-reserved-portion, and a photoresist-completely-removed-region; wherein the photoresist in the first photoresist-reserved-portion is completely reserved, the photoresist in the second photoresist-reserved-portion and the third photoresist-reserved-portion are partially reserved, a thickness of the photoresist in the second photoresist-reserved-portion is smaller than that in the first photoresist-reserved-portion, a thickness of the photoresist in the third photoresist-reserved-portion is smaller than that in the second photoresist-reserved-portion, the first photoresist-reserved-portion at least corresponds to a region for forming the source electrode and the drain electrode, the second photoresist-reserved-portion corresponds to a region for forming a channel, and the third photoresist-reserved-portion at least corresponds to a region for forming a pixel electrode, and the photoresist at a position of the via hole in the connection region is completely removed;
etching at least the source-drain metal film, the active layer film and a portion of the gate insulating film located in the photoresist-completely-removed-region;
performing an aching treatment on the first photoresist-reserved-portion, the second photoresist-reserved-portion and the third photoresist-reserved-portion to remove the third photoresist-reserved-portion;
etching at least the source-drain metal film located in the third photoresist-reserved-portion;
performing an aching treatment on the first photoresist-reserved-portion and the second photoresist-reserved-portion to remove the second photoresist-reserved-portion;
etching at least the source-drain metal film located in the second photoresist-reserved-portion; and
stripping remaining photoresist.

4. The fabrication method according to claim 3 , wherein the photoresist in the first photoresist-reserved-portion is completely reserved and has a thickness smaller than 1.5 lm.

5. The fabrication method according to claim 3 , wherein the thickness of the photoresist in the second photoresist-reserved-portion is 70% of that in the first photoresist-reserved-portion.

6. The fabrication method according to claim 3 , wherein the thickness of the photoresist in the third photoresist-reserved-portion is 30%-40% of that in the first photoresist-reserved-portion.

7. The fabrication method according to claim 3 , wherein the first photoresist-reserved-portion further corresponds to a region in the connection region except the via hole.

8. The fabrication method according to claim 3 , wherein the third photoresist-reserved-portion further corresponds to the isolation region.

9. The fabrication method according to claim 3 , wherein
the source-drain metal film, the active layer film and the portion of the gate insulating film located in the photoresist-completely-removed-region are etched; and
the etching at least the source-drain metal film located in the second photoresist-reserved-portion is: etching the source-drain metal film and a portion of the active layer film located in the second photoresist-reserved-portion, and at the same time, etching away the gate insulating film reserved in the photoresist-completely-removed-region.

10. The fabrication method according to claim 3 , wherein
the etching at least the source-drain metal film, the active layer film, and the portion of the gate insulating film located in the photoresist-completely-removed-region is:
removing the source-drain metal film located in the photoresist-completely-removed-region by wet etching;
removing the active layer film and the portion of the gate insulating film in the photoresist-completely-removed-region by dry etching.

11. The fabrication method according to claim 10 , wherein
removing the active layer film and the portion of the gate insulating film in the photoresist-completely-removed-region by dry etching is:
etching the active layer with SF 6 and CL 2 ; and
etching the gate insulating film with SF 6 and O 2 after the active layer film has been etched.

12. The fabrication method according to claim 11 , wherein an inert gas is added in the case that the active layer is etched with SF 6 and CL 2 .

13. The fabrication method according to claim 12 , wherein the inert gas is He.

14. The fabrication method according to claim 11 , wherein a pressure is maintained below 100 pa in the case that the active layer is etched with SF 6 and CL 2 .

15. The fabrication method according to claim 11 , wherein a total gas flow rate is controlled below 1500 sccm in the case that the active layer is etched with SF 6 and CL 2 .

16. The fabrication method according to claim 11 , wherein O 2 accounts for 40% or less of a gas mixture of SF 6 and O 2 in terms of gas flow rate in the case that the gate insulating film is etched with SF 6 and O 2 .

17. The fabrication method according to claim 11 , wherein a total gas flow rate is controlled below 1200 sccm in the case that the gate insulating film is etched with SF 6 and O 2 .

18. The fabrication method according to claim 1 , further comprising:
forming a pixel electrode and a common electrode on the base substrate, and the pixel electrode and the common electrode form an electric field therebetween.

19. The fabrication method according to claim 18 , wherein the pixel electrode and/or the common electrode comprise strip electrodes.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Guo Jian

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10P14/00 Primary

  Formation of materials, e.g. in the shape of layers or pillars · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D89/00

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title