Array substrates and optoelectronic devices

Patent metadata

Field	Value
Publication number	US-9466621-B2
Application number	US-201414166257-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Dec 16, 2010
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate;
a first conductive layer disposed on the substrate, wherein the first conductive layer comprises a gate electrode in a display region and a bottom conductive line in a peripheral region;
a second conductive layer disposed on the first conductive layer, wherein the second conductive layer comprises a source electrode and a drain electrode in the display region and a top conductive line in the peripheral region;
an insulation layer disposed between the first conductive layer and the second conductive layer; and
a semiconductor layer disposed between the second conductive layer and the insulation layer;
wherein the top conductive line connects to the bottom conductive line through a first contact hole,
wherein the source electrode, the drain electrode, and the top conductive line are composed of a same material.

2. The array substrate as claimed in claim 1 , wherein the second conductive layer is disposed on the bottom and the sidewall of the first contact hole.

3. The array substrate as claimed in claim 2 , wherein the second conductive layer disposed on the sidewall of the first contact hole contacts the insulation layer and the semiconductor layer.

4. The array substrate as claimed in claim 1 , wherein the first conductive layer comprises a bottom electrode in the display region, the second conductive layer comprises a top electrode in the display region, and the top electrode overlaps the bottom electrode.

5. The array substrate as claimed in claim 4 , wherein the insulation layer is disposed between the top electrode and the bottom electrode.

6. The array substrate as claimed in claim 5 , wherein the semiconductor layer is disposed between the top electrode and the insulation layer.

7. The array substrate as claimed in claim 1 , further comprising:
a passivation layer disposed on the second conductive layer; and
a pixel electrode disposed on the passivation layer;
wherein the pixel electrode connects to the source electrode or the drain electrode through a second contact hole.

8. The array substrate as claimed in claim 7 , wherein the pixel electrode is disposed on the bottom and the sidewall of the second contact hole.

9. The array substrate as claimed in claim 8 , wherein the pixel electrode disposed on the sidewall of the second contact hole contacts the passivation layer.

10. The array substrate as claimed in claim 7 , wherein the first conductive layer comprises a bottom electrode in the display region, and the second conductive layer comprises a top electrode in the display region, and the top electrode overlaps the bottom electrode.

11. The array substrate as claimed in claim 10 , wherein the pixel electrode connects to the top electrode through a third contact hole.

12. The array substrate as claimed in claim 11 , wherein the pixel electrode is disposed on the bottom and the sidewall of the third contact hole.

13. The array substrate as claimed in claim 12 , wherein the pixel electrode disposed on the sidewall of the third contact hole contacts the passivation layer.

14. The array substrate as claimed in claim 1 , wherein a channel of the semiconductor layer is disposed between the gate electrode, the source electrode, and the drain electrode.

15. The array substrate as claimed in claim 14 , wherein the channel of the semiconductor layer comprises metal oxide.

16. The array substrate as claimed in claim 1 , wherein one of the first conductive layer and the second conductive layer comprises aluminum or copper.

17. The array substrate as claimed in claim 1 , wherein the first conductive layer comprises a gate line contacted to the gate electrode, and the second conductive layer comprises a data line contacted to one of the source electrode or the drain electrode.

Assignees

• Innolux Corp

Inventors

• Chou Cheng-Hsu

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title