Systems and methods for high-speed, low-profile memory packages and pinout designs

Patent metadata

Field	Value
Publication number	US-9466571-B2
Application number	US-201514802750-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Mar 13, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

First claim

What is claimed is:

1. A stacked semiconductor package comprising:
an integrated circuit (“IC”) package substrate comprising a plurality of conductive contacts formed on a bottom surface of the IC package substrate, wherein the plurality of conductive contacts further comprise a plurality of data I/O contacts and a plurality of ground (“GND”) contacts;
an arrow-shaped die stack coupled to a top surface of the IC package substrate opposite the bottom surface, the arrow-shaped die stack comprising:
a first subset of stacked semiconductor dies having exposed surfaces closer to a first edge of the IC package substrate; and
a second subset of stacked semiconductor dies having exposed surfaces closer to a second edge of the IC package substrate;

wherein a first subset of the plurality of conductive contacts is communicatively coupled to the exposed surfaces of the first subset of stacked semiconductor dies, and wherein a second subset of the plurality of conductive contacts is communicatively coupled to the exposed surfaces of the second subset of stacked semiconductor dies, wherein only two GND contacts of the plurality of GND contacts are surrounded by the data I/O contacts associated with respective ones of the first and second subsets of the plurality conductive contacts.

2. The stacked semiconductor package of claim 1 , further comprising a plurality of electrically conductive vias extending through the IC package substrate, electrically coupling the plurality of conductive contacts to a plurality of electrically conductive bond pads arranged on the top surface of the IC package substrate.

3. The stacked semiconductor package of claim 2 , wherein:
the first subset of the plurality of conductive contacts, corresponding to a first communications channel, is arranged on a first side of the bottom surface of the IC package substrate; and
the second subset of the plurality of conductive contacts, corresponding to a second communications channel, is arranged on a second side of the bottom surface of the IC package substrate.

4. The stacked semiconductor package of claim 1 , wherein the arrow-shaped die stack comprises non-volatile memory dies.

5. The stacked semiconductor package of claim 1 , further comprising a memory controller die coupled between the arrow-shaped die stack and the top surface of the IC package substrate.

6. The stacked semiconductor package of claim 5 , wherein the memory controller die is flip-chip bonded to the top surface of the IC package substrate.

7. The stacked semiconductor package of claim 5 , wherein the memory controller die is wire bonded to electrically conductive bond pads formed on the top surface of the IC package substrate.

8. The stacked semiconductor package of claim 1 , wherein:
the first subset of stacked semiconductor dies forms a staircase in a first direction;
the second subset of stacked semiconductor dies forms a staircase in a second direction opposite the first direction;
the second subset of stacked semiconductor dies is stacked on top of the first subset of stacked semiconductor dies; and
each semiconductor die of the second subset of stacked semiconductor dies is rotated 180° from each die of the first subset of stacked semiconductor dies.

9. The stacked semiconductor package of claim 1 , wherein the IC package substrate comprises one of a land grid array (“LGA”), ball grid array (“BGA”), and a pin grid array (“PGA”).

Assignees

• Apple Inc

Inventors

• Fai Anthony
• Boyle Evan R
• Yang Zhiping
• Wu Zhonghua

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W42/271

  the arrangements being between stacked chips · CPC title