Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer

Patent metadata

Field	Value
Publication number	US-9466552-B2
Application number	US-201213436665-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

First claim

What is claimed is:

1. A vertical semiconductor device, comprising:
a silicon carbide substrate or a sapphire substrate having a first surface and a second surface facing opposite directions;
a conductive array formed by a plurality of conductive plugs which extend from the first surface completely through the substrate to the second surface;
a semiconductor layer formed on and in contact with the first surface, the semiconductor layer having a third surface and a fourth surface facing opposite directions, wherein the fourth surface faces the first surface;
a first electrode formed on and in contact with the third surface; and
a second electrode formed on and in contact with the second surface, for electrically connecting to the conductive array,
wherein the semiconductor layer includes:
a GaN layer doped with first conductive type impurities;
a base region doped with second conductive type impurities, the base region being formed in the GaN layer and electrically connected to the first electrode; and
an emitter region doped with first conductive type impurities, the emitter region being formed in the base region and electrically connected to a third electrode which is formed on the third surface;
wherein the first electrode, the semiconductor layer, the third electrode, the conductive array, and the second electrode form a vertical bipolar junction transistor (BJT).

2. A vertical semiconductor device, comprising:
a silicon carbide substrate or a sapphire substrate having a first surface and a second surface facing opposite directions;
a conductive array formed by a plurality of conductive plugs which extend from the first surface completely through the substrate to the second surface;
a semiconductor layer formed on and in contact with the first surface, the semiconductor layer having a third surface and a fourth surface facing opposite directions, wherein the fourth surface faces the first surface;
a first electrode formed on and in contact with the third surface; and
a second electrode formed on and in contact with the second surface, for electrically connecting to the conductive array,
wherein the semiconductor layer includes:
a GaN layer doped with first conductive type impurities;
a body region doped with second conductive type impurities, the body region being formed in the GaN layer and electrically connected to the first electrode;
an emitter region doped with first conductive type impurities, the emitter region being formed in the body region and electrically connected to the first electrode; and
an injection region doped with second conductive type impurities, the injection region being formed between the GaN layer and the substrate, and being electrically connected to the second electrode by the conductive array;
and the vertical semiconductor device further includes:
a dielectric layer formed on the third surface; and
a gate formed on the dielectric layer;

wherein the first electrode, the semiconductor layer, the conductive array, the second electrode, the dielectric layer, and the gate form a vertical insulated gate bipolar transistor (IGBT).

Assignees

• Chiu Chien-Wei
• Huang Tsung-Yi
• Richtek Technology Corp

Inventors

• Chiu Chien-Wei
• Huang Tsung-Yi

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D12/032

  of vertical IGBTs · CPC title

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title