Micro-electro mechanical system (MEMS) structures with through substrate vias and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9466532-B2
Application number	US-201213429029-A
Country	US
Kind code	B2
Filing date	Mar 23, 2012
Priority date	Jan 31, 2012
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures.

First claim

What is claimed is:

1. A device comprising:
a capping substrate having a cavity, wherein the capping substrate has a first surface of silicon; and
a substrate structure, wherein the substrate structure includes at least one micro-electro mechanical system (MEMS) device, wherein the MEMs device is disposed in the cavity, and wherein the substrate structure includes a layer providing a second surface of silicon;
wherein the first surface of silicon interfaces the second surface of silicon to form a fusion bond interface between the substrate structure and the capping substrate wherein the fusion bond interface is between the silicon of the first surface and silicon of the second surface;
at least one cavity surrounding at least a portion of the MEMS device;
at least one through substrate via (TSV) extending through the capping substrate and the fusion bond interface to contact the substrate structure, wherein the TSV comprises a central region free of conductive material and wherein the TSV provides an electrical connection to an integrated circuit component; and
a polymer material in the central region of the TSV.

2. The device of claim 1 , wherein the substrate structure includes at least one dielectric layer, wherein the at least one cavity includes is formed by etching the at least one dielectric layer.

3. The device of claim 1 , wherein the substrate structure includes a MEMS substrate having the MEMS device and an integrated circuit substrate having an integrated circuit.

4. The device of claim 1 , wherein the device includes the polymer material over the capping substrate.

5. The device of claim 1 , wherein a bonding layer including the fusion bond interface has a thickness in a range from about 10 Å to about 2000 Å.

6. The device of claim 1 , wherein the TSV has a width in a range from about 10 microns (μm) to about 150 μm.

7. The device of claim 1 , wherein a bonding structure is formed over the TSV, and wherein the bonding structure is disposed over and comes in contact with a metal layer used to fill the TSV.

8. The device of claim 1 , wherein the TSV extends through the capping substrate, wherein the interface of the first surface of silicon and the second surface of silicon comprises a first portion and a second portion discontinuous with the first portion, the TSV extending through the first portion of the fusion bonding layer, and the second portion of the fusion bonding layer being free of the TSV.

9. The device of claim 1 , wherein the capping substrate includes an integrated circuit.

10. A method of forming a micro-electro mechanical system (MEMS) structure, the method comprising:
providing a first substrate structure having a first layer with a first silicon surface;
providing a second substrate having a second layer with a second silicon surface;
bonding the second substrate structure to the first substrate structure using fusion bonding at a temperature between about 500 Celsius and 1200 Celsius, wherein the fusion bonding fuses the first layer and the second layer by fusing the first and second silicon surfaces to form a fusion bonding interface, wherein the second substrate structure includes at least one micro-electro mechanical system (MEMS) device, and wherein there is at least one cavity surrounding at least a portion of the MEMS device;
thinning the first substrate to provide a first surface of the thinned first substrate; and
forming a TSV in the first substrate structure and through the fusion bonding interface between the first substrate and the second substrate such that a metal layer of the TSV extends through the fusion bonding interface, wherein the forming the TSV includes forming an isolation layer directly on the first surface of the thinned first substrate.

11. The method of claim 10 , further comprising:
forming an under bump metallurgy (UBM) layer over the first substrate structure, wherein the UBM layer contacts the metal layer used to fill the TSV.

12. The method of claim 10 , wherein bonding the second substrate to the first substrate comprises forming a bonding ratio in a range from about 40% to about 95%.

13. The method of claim 10 , further comprising, prior to the fusing the first silicon surface and the second silicon surface, making the first and second silicon surfaces hydrophobic.

14. A method of forming a micro-electro mechanical system (MEMS) structure, the method comprising:
providing a first substrate structure having a first layer with a first silicon surface;
providing a second substrate having at least one micro-electro mechanical system (MEMS) device and having a second layer with a second silicon surface;
fusion bonding the second substrate structure to the first substrate structure, wherein the fusion bonding includes:
pressing together the first and second silicon surfaces;
annealing the pressed together first and second silicon surfaces; and
thereby forming a bonding interface between the first and second silicon surfaces; and

forming an interconnect through the first substrate and the bonding interface to contact the second substrate.

15. The method of claim 14 , wherein the annealing is performed at between about 900 Celsius and 1200 Celsius.

16. The method of claim 14 , wherein the forming the interconnect includes
forming an opening in the first substrate structure and the bonding interface; and
depositing a conductive material in the opening to form a through silicon via (TSV).

17. The method of claim 16 , wherein the forming the interconnect further includes doping a region of the second substrate, the doped region being disposed in the opening.

18. The method of claim 17 , wherein the depositing the conductive material includes forming an interface between the conductive material and the doped region.

19. The method of claim 14 , further comprising:
making the first silicon surface and the second silicon surface hydrophobic prior to the fusion bonding.

20. The method of claim 14 , further comprising: thinning the first substrate after the fusion bonding and prior to forming the interconnect.

Assignees

• Chu Chia-Hua
• Chang Kuei-Sung
• Lee Te-Hao
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Chia-Hua
• Chang Kuei-Sung
• Lee Te-Hao

Classifications

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• B82Y30/00

  Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title

• B81C1/00269

  Bonding of solid lids or wafers to the substrate · CPC title

• B81B2207/095

  through the lid · CPC title

• B81B2207/07

  Interconnects · CPC title