Masking method for semiconductor devices with high surface topography

Patent metadata

Field	Value
Publication number	US-9466529-B2
Application number	US-201414766412-A
Country	US
Kind code	B2
Filing date	Jan 29, 2014
Priority date	Feb 8, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

The method comprises the steps of providing a semiconductor body or substrate ( 1 ) with a recess or trench ( 2 ) in a main surface ( 10 ), applying a mask ( 3 ) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity ( 4 ), which is filled with a gas, and forming at least one opening ( 5 ) in the mask at a distance from the recess or trench, the distance ( 6 ) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.

First claim

The invention claimed is:

1. A method of producing a semiconductor device, comprising:
providing a semiconductor body or substrate having a main surface with a recess or trench in the main surface;
applying a mask above the main surface, the mask covering the recess or trench, so that the recess or trench and the mask form a closed cavity, which is filled with a gas; and
forming a plurality of openings in the mask, the openings being arranged on the periphery of the recess at a distance from the recess or trench, the distance being adapted to allow the gas to escape from the cavity via the openings when the difference between a pressure exerted on the mask by the gas and a pressure exerted on the mask from outside the recess or trench is larger than a predefined value.

2. The method of claim 1 , wherein the mask is applied as a dry film using a lamination technique.

3. The method of claim 1 , wherein the mask forms a planar layer above the recess or trench.

4. The method of claim 1 , wherein the distance is less than 5 μm.

5. The method of claim 1 , wherein the distance is less than 3 μm.

6. The method of claim 1 , wherein the gas filling the cavity is captured ambient air.

7. The method of claim 1 , wherein the gas filling the cavity is nitrogen.

8. A method of producing a semiconductor device, comprising:
providing a semiconductor body or substrate having a main surface with a recess or trench in the main surface;
applying a mask above the main surface, the mask covering the recess or trench, so that the recess or trench and the mask form a closed cavity, which is filled with a gas; and
forming at least one opening in the mask at a distance from the recess or trench, the distance being adapted to allow the gas to escape from the cavity via the at least one opening when the difference between a pressure exerted on the mask by the gas and a pressure exerted on the mask from outside the recess or trench is larger than a predefined value,
wherein the recess or trench is provided for a through-wafer via or contact comprising a metal layer, and
wherein the metal layer is applied to an area of the main surface surrounding the recess or trench, and the mask is used in an etching step to structure the metal layer, so that the at least one opening is transferred to the metal layer.

9. The method of claim 8 , wherein
the at least one opening is locally confined in such a manner that the metal layer extends from the recess or trench beyond the at least one opening.

10. The method of claim 8 , wherein
the metal layer is structured by etching,
a further layer is applied,
the mask is applied on the further layer, and
the mask is used to structure the further layer.

11. The method of claim 10 , wherein
the further layer is a passivation layer, which is also applied in the recess or trench.

Assignees

• Ams Ag

Inventors

• Koppitsch Guenther
• Stueckler Ewald
• Rohracher Karl
• Teva Jordi

Classifications

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/059 Primary

  by reflowing or applying pressure · CPC title