Multilayer device and manufacturing method of the same

US9466416B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9466416-B2
Application numberUS-201414496034-A
CountryUS
Kind codeB2
Filing dateSep 25, 2014
Priority dateMay 21, 2012
Publication dateOct 11, 2016
Grant dateOct 11, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer inductor device in which parasitic inductance is made smaller while preventing increase in a mounting area of the device and complexity of a wiring pattern, and a manufacturing method of the stated multilayer inductor device. An outer electrode and a terminal electrode are connected to each other through a via hole. A side surface of a non-magnetic member forms a part of an end surface of the device, while the other side surface thereof being in contact with the via hole. A side surface of the via hole that makes contact with the non-magnetic member is opened, which prevents the parasitic inductance from being increased. The via hole being provided in an arbitrary position makes it possible to prevent the wiring pattern from being complicated and a mounting area of the device from being increased.

First claim

Opening claim text (preview).

The invention claimed is: 1. A multilayer device comprising: a multilayer body in which a plurality of substrates including magnetic-member substrates are laminated; a first land electrode being provided on an uppermost surface of the multilayer body; a second land electrode being provided on a lowermost surface of the multilayer body; a via hole provided inside a magnetic member layer of the multilayer body and electrically connecting the first land electrode and the second land electrode to each other; and a non-magnetic member extending from the uppermost surface to the lowermost surface and contacting with the via hole. 2. An electronic component module comprising: the multilayer device according to claim 1 ; and an electronic component mounted on the first land electrode.

Assignees

Inventors

Classifications

  • Surface mounted devices · CPC title

  • Printed circuit coils (apparatus or processes for manufacturing printed circuits in general H05K3/00) · CPC title

  • with stacked layers · CPC title

  • by forming conductive walled aperture in base · CPC title

  • Printed windings · CPC title

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Frequently asked questions

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What does patent US9466416B2 cover?
A multilayer inductor device in which parasitic inductance is made smaller while preventing increase in a mounting area of the device and complexity of a wiring pattern, and a manufacturing method of the stated multilayer inductor device. An outer electrode and a terminal electrode are connected to each other through a via hole. A side surface of a non-magnetic member forms a part of an end sur…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01F17/0013. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).