Server on a chip and node cards comprising one or more of same

Patent metadata

Field	Value
Publication number	US-9465771-B2
Application number	US-201213662759-A
Country	US
Kind code	B2
Filing date	Oct 29, 2012
Priority date	Sep 24, 2009
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.

First claim

The invention claimed is:

1. A server on a chip (SoC), comprising:
a node central processing unit (CPU) subsystem that includes a plurality of processing cores;
a peripheral subsystem that includes a plurality of peripheral controllers;
a system interconnect subsystem configured to provide packet switch functionality within the SoC and between the SoC and at least one other SoC that is connected to the SoC; and
a management subsystem coupled to the node CPU subsystem, the peripheral subsystem, and the system interconnect subsystem, wherein the management subsystem includes a management processor that is configured to run an operating system to manage operational functionality of the node CPU subsystem, the peripheral subsystem, and the system interconnect subsystem,
wherein the operating system run by the management processor includes a plurality of application tasks, an operating system (OS)/input-output (I/O) abstraction layer, a real-time operating system (RTOS), and a plurality of device drivers, wherein the plurality of application tasks includes boot task, system management task, power management task, serial concentrator task, frame switch management task, and network proxy task.

2. The SoC of claim 1 , wherein:
the node CPU subsystem includes a plurality of node CPU subsystem power domains,
the peripheral subsystem includes a plurality of peripheral subsystem power domains,
the system interconnect subsystem includes a plurality of system interconnect subsystem power domains; and
the management processor is configured to manage one or more activities within each of the node CPU subsystem power domains, the peripheral subsystem power domains, and the system interconnect subsystem power domains that influence power consumption therein.

3. The SoC of claim 2 , wherein:
the management processor is configured to cause each of the node CPU subsystem power domains, the peripheral subsystem power domains, and the system interconnect subsystem power domains to be selectively transitioned between at least two different power states; and
wherein functionality of at least one operational component of one of the subsystems associated with a respective power domain is configured to transition to a reduced power consumption state in response to the respective power domain being transitioned from a first power state to a second power state.

4. The SoC of claim 3 , wherein:
the plurality of processing cores are within separate node CPU subsystem power domains;
at least two of the plurality of peripheral controllers are within separate peripheral subsystem power domains;
at least two XAUI links of the system interconnect subsystem are within separate system interconnect subsystem power domains.

5. The SoC of claim 1 , wherein the management subsystem is configured to:
manage power consumption on a per-power domain basis;
act as proxy for the plurality of processing cores for interrupts intended for reception by the plurality of processing cores; and
control a configuration of a variable internal supply used to supply electrical power to the node CPU subsystem.

6. The SoC of claim 1 , wherein the management subsystem is configured to:
selectively transition a first clock to the management processor between a first on-state and a first off-state;
selectively transition a second clock to one or more private peripherals of the management processor between a second on-state and a second off-state; and
selectively transition a third clock to one or more shared peripherals of the management processor between a third on-state and a third off-state.

7. The SoC of claim 6 , wherein the management subsystem is configured to:
manage power consumption of a per-power domain basis;
act as proxy for the plurality of processing cores for interrupts intended for reception by the plurality of processing cores; and
control a configuration of a variable internal supply used to supply electrical power to the node CPU subsystem.

8. The SoC of claim 1 , wherein:
the node CPU subsystem includes a cache memory, a main memory, and a main memory controller coupled between the cache memory and the main memory;
the cache memory is coupled to each of the plurality of processing cores thereby enabling the cache memory to be shared by all of the plurality of processing cores;
the main memory controller is configured to support error code correction (ECC) functionality; and
the peripheral subsystem includes one or more Ethernet controllers and one or more serial advanced technology attachment (SATA) controllers.

9. The SoC of claim 8 , wherein the peripheral subsystem further includes:
one or more flash controllers; and
one or more peripheral component interconnect express (PCIe) controllers.

10. The SoC of claim 8 , wherein:
the node CPU subsystem includes a plurality of node CPU subsystem power domains,
the peripheral subsystem includes a plurality of peripheral subsystem power domain,
the system interconnect subsystem includes a plurality of system interconnect subsystem power domains; and
the management processor is configured to manage one or more activities within each of the node CPU subsystem power domain, the peripheral subsystem power domain, and the system interconnect subsystem power domains that influence power consumption therein.

11. The SoC of claim 10 , wherein:
the management processor is configured to cause each of the node CPU subsystem power domains, the peripheral system power domains, and the system interconnect subsystem power domains to be selectively transitioned between at least two different power states; and
wherein functionality of at least one operational component of one of the subsystems associated with a respective power domain is transitioned to a reduced power consumption state in response to the respective power domain being transitioned from a first power state to a second power state.

12. The SoC of claim 8 , wherein the management subsystem is configured to:
manage power consumption on a per-power domain basis;
act as proxy for the plurality of processing cores for interrupts intended for reception by the plurality of processing cores; and
control a configuration of a variable internal supply used to supply electrical power to the node CPU subsystem.

13. A node card, comprising:
a node card substrate that includes circuitry configured to enable communication of information between the node card and one or more other node cards; and
a plurality of server on a chip (SoC) units mounted on the node card substrate and electrically connected to the circuitry of the node card substrate, wherein each of the SoC units defines an instance of a SoC node of the node card, wherein each SoC node includes a SoC that comprises:
a node CPU subsystem,
a peripheral subsystem,
a system interconnect subsystem, and
a management subsystem coupled to the node CPU subsystem, the peripheral subsystem, and the system interconnect subsystem, wherein the management subsystem includes a management processor that is configured to run an operating system to manage operational functionality of the node CPU subsystem, the peripheral subsystem, and the system interconnect subsystem,

wherein the operating system run by the management processor includes a plurality of application tasks, an operating system (OS)/input-output (I/O) abstraction layer, a real-time operating system (RTOS), and a plurality of device drivers, wherein the plurality of application tasks includes boot task, system management task, power management task, serial concentrator task, frame switch management task, and network proxy task.

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Assignees

• Iii Holdings 2 Llc

Inventors

• Davis Mark Bradley
• Borland David James
• Schnell Arnold Thomas

Classifications

• G06F15/7803 Primary

  System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades · CPC title

• Y02B60/1207

  Cross-Sectional Technologies · mapped topic

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F15/7807 Primary

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title