Verification of management of real storage via multi-threaded thrashers in multiple address spaces

Patent metadata

Field	Value
Publication number	US-9465736-B2
Application number	US-201615090890-A
Country	US
Kind code	B2
Filing date	Apr 5, 2016
Priority date	May 28, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.

First claim

What is claimed is:

1. A method of verifying management of real storage in a computing system via multi-threaded thrashers in multiple address spaces, the method comprising:
dynamically scaling a number of units of work and a number of address spaces based on a number of available processors, each of the units of work representing a respective function to be executed and each of the address spaces identifying a contiguous range of virtual addresses, the dynamically scaling the number of units of work including assigning each of the units of work to a respective one of the available processors;
dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the units of work based on a total available memory, the dynamically scaling the amount and page sizes of virtual storage including determining the total available memory as a sum of total amount of real storage, total amount of direct access storage device (DASD) auxiliary storage, and total amount of storage class memory (Flash) auxiliary storage;
obtaining, at each of the units of work using the respective one of the available processors in parallel, a range of the virtual storage located in different types of storage frame sizes and attributes, a storage frame being a subset of the real storage, and real memory, represented by a sum of the range of the virtual storage accessed by each of the units of work, exceeding the real storage;
accessing, using each of the units of work, the storage pages corresponding with the respective different types of storage frame sizes and attributes to perform the respective function; and
verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function to perform deterministic validation, wherein the verifying the content of the storage pages includes using a unique key composed of a corresponding frame address of the location, a sequence number, and a stored clock time.

Assignees

• IBM

Inventors

• Foster Alfred F
• Miller Jr Robert
• Rankin Thomas F

Classifications

• G06F3/0644 Primary

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F2212/652

  Page size control · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F12/0623 Primary

  for memory modules · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title