Systems, apparatuses, and methods for performing delta encoding on packed data elements

Patent metadata

Field	Value
Publication number	US-9465612-B2
Application number	US-201113976427-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Embodiments of systems, apparatuses, and methods for performing delta encoding on packed data elements of a source and storing the results in packed data elements of a destination using a single vector packed delta encode instruction are described.

First claim

What is claimed is:

1. A method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a processor core; and
executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements and no other elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value of that packed data element minus a packed data element that is of immediate lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

2. The method of claim 1 , wherein the source and destination operands are stored in vector registers.

3. The method of claim 2 , wherein the vector registers are 128-bits, 256-bits, or 512-bits in size.

4. The method of claim 1 , wherein the packed data elements are 32-bits in size.

5. The method of claim 1 , wherein each calculated value is calculated by adding a negative version of the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

6. The method of claim 1 , wherein each calculated value is calculated by subtracting the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

7. The method of claim 1 , wherein the executing comprises:
storing the first packed data element from a least significant packed data element position of the source operand into a corresponding least significant packed data element position of the destination operand.

8. An apparatus comprising:
a hardware decoder to decode a single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements and no other elements into a decoded single instruction; and
an execution unit to execute the decoded single instruction to calculate for each packed data element position of the source operand, other than a first packed data element position, a value of that packed data element minus a packed data element that is of immediate lesser significance and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element of the source operand, and store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand.

9. The apparatus of claim 8 , further comprising:
a plurality of vector registers, wherein the source and destination operands are to be stored in vector registers.

10. The apparatus of claim 9 , wherein the vector registers are 128-bits, 256-bits, or 512-bits in size.

11. The apparatus of claim 8 , wherein the packed data elements are 32-bits in size.

12. The apparatus of claim 8 , wherein each calculated value is to be calculated by subtracting the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

13. The apparatus of claim 8 , wherein each calculated value is to be calculated by adding a negative version of the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

14. The apparatus of claim 8 , wherein the execution unit is to store the first packed data element from a least significant packed data element position of the source operand into a corresponding least significant packed data element position of the destination operand.

15. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a processor core; and
executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements and no other elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value of that packed data element minus a packed data element that is of immediate lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

16. The non-transitory machine readable medium of claim 15 , wherein the source and destination operands are stored in vector registers.

17. The non-transitory machine readable medium of claim 15 , wherein the packed data elements are 32-bits in size.

18. The non-transitory machine readable medium of claim 15 , wherein each calculated value is calculated by adding a negative version of the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

19. The non-transitory machine readable medium of claim 15 , wherein each calculated value is calculated by subtracting the packed data element that is of immediate lesser significance to the packed data element of the packed data element position.

20. The non-transitory machine readable medium of claim 15 , wherein the executing comprises storing the first packed data element from a least significant packed data element position of the source operand into a corresponding least significant packed data element position of the destination operand.

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Willhalm Thomas
• Drysdale Tracy Garrett
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Willhalm Thomas
• Drysdale Tracy Garrett

Classifications

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title