Operation management in a memory device

Patent metadata

Field	Value
Publication number	US-9465539-B2
Application number	US-201514943113-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Jun 28, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
performing a first memory operation having an associated timing requirement;
after completing the first memory operation, determining a timing margin between completion of the first memory operation and expiration of its associated timing requirement;
comparing the timing margin between completion of the first memory operation and expiration of its associated timing requirement to a length of time to perform a particular portion of a second memory operation;
performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation;
after completing the particular portion of the second memory operation, determining a timing margin between completion of the particular portion of the second memory operation and the expiration of the associated timing requirement of the first memory operation;
comparing the timing margin between completion of the particular portion of the second memory operation and the expiration of the associated timing requirement of the first memory operation to a length of time to perform a different portion of the second memory operation; and
performing the different portion of the second memory operation between completion of the particular portion of the second memory operation and the expiration of the associated timing requirement of the first memory operation if it is determined that the timing margin between completion of the particular portion of the second memory operation and the expiration of the associated timing requirement of the first memory operation exceeds the length of time to perform the different portion of the second memory operation.

2. The method of claim 1 , wherein performing the first memory operation is in response to a command received by the memory device.

3. The method of claim 2 , wherein performing the particular portion of the second memory operation comprises performing a portion of a background operation.

4. The method of claim 2 , wherein performing the particular portion of the second memory operation comprises initiating the particular portion of the second memory operation by an internal controller of the memory device.

5. The method of claim 4 , wherein performing the particular portion of the second memory operation comprises performing the particular portion of the second memory operation hidden from any external controller connected to the memory device.

6. The method of claim 1 , wherein performing the first memory operation comprises performing the first memory operation as part of a reset sequence of the memory device.

7. The method of claim 1 , further comprising:
storing an indication that the particular portion of the second memory operation has been performed after completion of the particular portion of the second memory operation.

8. The method of claim 1 , further comprising:
performing a third memory operation having an associated timing requirement;
after completing the third memory operation, determining a timing margin between completion of the third memory operation and expiration of its associated timing requirement;
comparing the timing margin between completion of the third memory operation and expiration of its associated timing requirement to a length of time to perform a an additional portion of the second memory operation; and
performing the additional portion of the second memory operation between completion of the third memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the third memory operation and expiration of its associated timing requirement exceeds the length of time to perform the additional portion of the second memory operation.

9. The method of claim 8 , wherein performing the third memory operation is in response to a command received by the memory device.

10. The method of claim 8 , further comprising:
storing an indication that the particular portion of the second memory operation has been performed after completion of the particular portion of the second memory operation;
storing an indication that the different portion of the second memory operation has been performed after completion of the different portion of the second memory operation; and
storing an indication that the additional portion of the second memory operation has been performed after completion of the additional portion of the second memory operation.

11. A method of operating a memory device, the method comprising:
performing a first memory operation having an associated timing requirement;
after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a portion of a second memory operation;
performing the portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the portion of the second memory operation; and
for one or more additional portions of the second memory operation:
reading a state tracker storing status information indicating a next portion of the second memory operation to be performed;
determining whether a timing margin between completion of the preceding portion of the second memory operation and expiration of the associated timing requirement of the first memory operation exceeds a length of time to perform the next portion of the second memory operation; and
performing the next portion of the second memory operation between completion of the preceding portion of the second memory operation and expiration of the associated timing requirement of the first memory operation if it is determined that the timing margin between completion of the preceding portion of the second memory operation and expiration of the associated timing requirement of the first memory operation exceeds the length of time to perform the next portion of the second memory operation.

12. The method of claim 11 , further comprising:
after expiration of the associated timing requirement of the first memory operation, performing a third memory operation having an associated timing requirement;
reading the state tracker storing the status information indicating a next subsequent portion of the second memory operation to be performed;
after completing the third memory operation, determining whether a timing margin between completion of the third memory operation and expiration of its associated timing requirement exceeds a length of time to perform the next subsequent portion of the second memory operation; and
performing the next subsequent portion of the second memory operation between completion of the third memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the third memory operation and expiration of its associated timing requirement exceeds the length of time to perform the next subsequent portion of the second memory operation.

13. The method of claim 11 , wherein reading the state t

Assignees

• Micron Technology Inc

Inventors

• Cabrera Anthony R
• Hendrickson Nicholas
• Melcher Robert

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title