AVS master slave

Patent metadata

Field	Value
Publication number	US-9465396-B2
Application number	US-201313874924-A
Country	US
Kind code	B2
Filing date	May 1, 2013
Priority date	May 1, 2012
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Aspects of the disclosure provide an integrated circuit (IC). The IC includes an input interface and a controller. The input interface is configured to receive an input signal providing information for controlling a supply voltage based on a performance characteristic of another IC. The controller is configured to generate an output signal for controlling the supply voltage based on a combination of the input signal and a performance characteristic of the IC.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
an input interface configured to receive an input signal providing information for controlling a supply voltage based on a performance characteristic of another IC; and
a controller configured to generate an output signal for controlling the supply voltage based on a combination of the input signal and a performance characteristic of the IC, the controller including a feedback voltage generator configured to generate a feedback voltage signal by combining an offset voltage with the supply voltage to control a voltage regulator to regulate the supply voltage to the IC and to the other IC.

2. The circuit of claim 1 , wherein the input interface is configured to receive the input signal in a digital form.

3. The circuit of claim 1 , wherein the controller is configured to generate the output signal in a digital form for controlling the supply voltage based on the performance characteristic of the IC and the input signal, and to provide the output signal to a third IC.

4. The circuit of claim 1 , wherein the input interface is configured to receive the input signal for controlling the supply voltage of the other IC to meet a performance requirement.

5. The circuit of claim 1 , further comprising:
an output interface configured to output one of the output signal in a digital form, and the feedback voltage signal in an analog form.

6. The circuit of claim 1 , wherein:
a speed indicator is configured to generate a signal indicative of a speed of the IC; and
the controller is configured to generate the output signal based on the input signal and the signal indicative of the speed of the IC.

7. A method, comprising:
receiving by an integrated circuit (IC) an input signal from another IC, the input signal providing information for controlling a supply voltage based on a performance characteristic of the other IC;
generating a feedback voltage signal by combining an offset voltage with the supply voltage to control a voltage regulator to regulate the supply voltage to the IC and to the other IC based on the supply voltage and the input signal; and
generating an output signal based on a combination of the feedback voltage signal and a performance characteristic of the IC.

8. The method of claim 7 , wherein receiving by the IC the input signal from the other IC further comprises:
receiving the input signal in a digital form.

9. The method of claim 7 , wherein generating the output signal based on the input signal and the performance characteristic of the IC further comprise:
generating the output signal in a digital form; and
transmitting the output signal to a third IC.

10. The method of claim 7 , wherein receiving by the IC the input signal from the other IC further comprises:
receiving the input signal for controlling the supply voltage of the other IC to meet a performance requirement.

11. The method of claim 7 , further comprising at least one of:
configuring an output interface to output the output signal in a digital form;
configuring the output interface to output the feedback voltage signal in an analog form.

12. The method of claim 7 , further comprising:
generating a signal indicative of a speed of the IC; and
generating the output signal based on the input signal and the signal indicative of the speed of the IC.

13. A system, comprising:
a voltage regulator configured to regulate a supply voltage to multiple integrated circuits (ICs);
a first IC configured to output a first signal for controlling the supply voltage based on a performance characteristic of the first IC; and
a second IC configured to receive the first signal, and to generate a second signal for controlling the supply voltage based on a combination of the first signal and a performance characteristic of the second IC, the second IC including a feedback voltage generator configured to generate a feedback voltage signal by combining an offset voltage with the supply voltage to control a voltage regulator to regulate the supply voltage to the first IC and to the second IC.

14. The system of claim 13 , wherein the second IC is configured to receive the input signal in a digital form.

15. The system of claim 13 , wherein the second IC is configured to generate the output signal in a digital form for controlling the supply voltage based on the performance characteristic of the second IC and the input signal, and to provide the output signal to a third IC.

16. The system of claim 13 , wherein the input interface is configured to receive the input signal for controlling the supply voltage of the other IC to meet a performance requirement.

17. The system of claim 13 , wherein IC further comprises:
an output interface configured to output one of the output signal in a digital form, and the feedback voltage signal in an analog form.

Assignees

• Marvell Israel (M I S L) Ltd
• Marvell Israel (M I S L ) Ltd

Inventors

• Moshe Michael
• Ecker Reuven
• Bourstein Ido

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G05F1/625 Primary

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G05F1/10 Primary

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title