Array substrate and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9465264-B2
Application number	US-201314362241-A
Country	US
Kind code	B2
Filing date	Oct 12, 2013
Priority date	Mar 14, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

An array substrate and a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate ( 1 ); a thin film transistor, a passivation layer ( 5 ) and a transparent electrode ( 6 ), sequentially formed on the substrate, wherein a groove ( 51 ) is formed in an upper surface of the passivation layer ( 5 ), and the transparent electrode ( 6 ) is provided in the groove ( 51 ).

First claim

The invention claimed is:

1. A manufacturing method of an array substrate, comprising:
forming a thin film transistor and a passivation layer on a substrate, and the passivation layer covering the thin film transistor and being formed with a groove in a upper surface; and
forming a transparent electrode in the groove;
wherein the step of forming the groove in the upper surface of the passivation layer comprises:
forming the passivation layer on the substrate with the thin film transistor formed thereon;
coating a photoresist on the passivation layer, and exposing the photoresist through a double-tone mask, wherein the photoresist corresponding to a region where the transparent electrode is disposed is partly exposed, the photoresist corresponding to a region of a through hole exposing the drain electrode is completely exposed, and the photoresist in other regions is not exposed;
after a developing treatment, removing the completely exposed photoresist so that the passivation layer corresponding to the region of the through hole exposing the drain electrode is exposed, and then forming the through hole exposing the drain electrode by using an etching process;
removing the partly exposed photoresist by using an ashing process so that the passivation layer corresponding to the region of where the transparent electrode is disposed; and
partly removing the exposed passivation layer by using an etching process, so that the groove is formed in an upper surface of the passivation layer.

2. The manufacturing method of the array substrate according to claim 1 , wherein the forming the thin film transistor on the substrate comprises:
forming a gate electrode on the substrate through a patterning process;
forming a gate insulating layer on the gate electrode; and
forming an active layer and a source/drain electrode on the gate insulating layer through a patterning process.

3. The manufacturing method of an array substrate according to claim 1 , wherein the forming the transparent electrode in the groove comprises:
forming a transparent conductive layer on the substrate with the groove formed therein;
coating a photoresist on the transparent conductive layer;
performing an ashing treatment to the photoresist to retain the photoresist in the groove and remove the photoresist in regions other than the groove so as to expose the transparent conductive layer; and
removing the exposed transparent conductive layer and stripping the photoresist in the groove using an etching process, thereby forming the transparent electrode.

4. The manufacturing method of an array substrate according to claim 1 , wherein the transparent electrode serves as a pixel electrode.

5. The manufacturing method of an array substrate according to claim 1 , wherein the groove is formed in a comb shape, and the transparent electrode serves as a pixel electrode, before forming the passivation layer, the method further comprises: forming a common electrode.

6. The manufacturing method of an array substrate according to claim 1 , wherein the groove is formed in a comb shape, and the transparent electrode serves as a common electrode, before forming the passivation layer, the method further comprises: forming a pixel electrode.

7. A manufacturing method of an array substrate, comprising:
forming a thin film transistor and a passivation layer on a substrate, and the passivation layer covering the thin film transistor and being formed with a groove in a upper surface; and
forming a transparent electrode in the groove;
wherein the step of forming the groove in the upper surface of the passivation layer comprises:
forming a photosensitive resin layer on the substrate with the thin film transistor formed thereon;
exposing the photosensitive resin layer through a double-tone mask, so that the photosensitive resin layer corresponding to a region where the transparent electrode is disposed is partly exposed, the photosensitive resin layer corresponding to a region of the through hole exposing the drain electrode is completely exposed, and the photosensitive resin layer in other regions is not exposed;
partly removing the photosensitive resin layer corresponding to the region where the transparent electrode is disposed to form the groove and completely removing the photosensitive resin layer corresponding to the region of the through hole exposing the drain electrode to form the through hole by using a developing process.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Choi Seungjin
• Yoo Seongyeol
• Song Youngsuk

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G03F7/00

  Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor (using photoresist structures for special production processes, see the relevant places, e.g. B44C, H10P76/00, H05K) · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title