Enhanced ball grid array

Patent metadata

Field	Value
Publication number	US-9462691-B1
Application number	US-201414158660-A
Country	US
Kind code	B1
Filing date	Jan 17, 2014
Priority date	Jan 17, 2014
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A two-dimensional array of bonding pads is formed on a first major surface of a substrate. At least some of the pads are connected to conductors that extend across or into the substrate. The pads can be classified in two groups. A first group is conventional, each pad providing a continuous electrically conductive surface on which a solder ball or solder bump may be formed. In the second group, each pad has a plurality of isolated electrically conductive regions that are connected to different conductors that extend across or into the substrate. Solder balls or solder bumps having a first height are mounted on some of the pads. Multi-terminal devices that have a height that is no more than that of the first height are mounted on at least some of the second group of pads; and their terminals are connected to different electrically conductive regions.

First claim

What is claimed is:

1. A device package comprising:
a substrate having first and second major surfaces and electrical conductors extending across or into the substrate;
a two-dimensional array of pads formed on the first major surface of the substrate, first and second subsets of the pads being connected to the electrical conductors, each pad of the second subset of the pads having a plurality of isolated electrically conductive regions that are connected to different conductors;
solder balls or solder bumps formed on the first subset of the pads, said solder balls or solder bumps having a first height; and
other devices formed on the second subset of the pads that have a height that is no more than that of the first height, wherein each of the other devices is directly mounted on one of the second subset of the pads, wherein each of the other devices comprises multiple terminals, and wherein each of the multiple terminals of one of the other devices is electrically connected to a different one of the plurality of isolated electrically conductive regions of one of the second subset of the pads.

2. The package of claim 1 wherein the other devices include devices having two electrical terminals and the two terminals are connected to two isolated electrically conductive regions in certain of the pads of the second subset of pads.

3. The package of claim 1 wherein the other devices are selected from the group consisting of resistors, capacitors, and inductors.

4. The device of claim 1 wherein the other devices include devices having three electrical terminals and the three terminals are connected to three isolated electrically conductive regions in certain of the pads of the second subset of pads.

5. The package of claim 1 wherein the other devices include devices having four electrical terminals and the four terminals are connected to four isolated electrically conductive regions in certain of the pads of the second subset of pads.

6. The package of claim 1 wherein the other devices are selected from the group of active devices consisting of switches, sensors, accelerometers, regulators, interlocks, diodes, transistors, integrated circuits, MEMS devices, mechanical components, and warpage compensation circuits.

7. A device structure comprising:
a first substrate having first and second major surfaces and electrical conductors extending across or into the substrate;
a two-dimensional array of pads formed on the first major surface of the first substrate, first and second subsets of the pads being connected to the electrical conductors, each pad of the second subset of the pads having a plurality of isolated electrically conductive regions that are connected to different conductors;
solder balls or solder bumps formed on the first subset of the pads, said solder balls or solder bumps having a first height;
other devices formed on the second subset of the pads that have a height that is no more than the first height, wherein each of the other devices is directly mounted on one of the second subset of the pads, wherein each of the other devices comprises multiple terminals, and wherein each of the multiple terminals of each of the other devices is electrically connected to a different one of the plurality of isolated electrically conductive regions of a corresponding one of the second subset of the pads;
a second substrate having first and second major surfaces; and
electrical conductors formed on the first major surface of the second substrate and in contact with the solder balls or solder bumps formed on the first set of pads on the first substrate.

8. The device structure of claim 7 wherein the other devices include devices having two electrical terminals and the two terminals are connected to two isolated electrically conductive regions in certain of the pads of the second subset of pads.

9. The device structure of claim 7 wherein the other devices are selected from the group consisting of resistors, capacitors and inductors.

10. The device structure of claim 7 wherein the other devices include devices having three electrical terminals and the three terminals are connected to three isolated electrically conductive regions in certain of the pads of the second subset of pads.

11. The device structure of claim 7 wherein the other devices include devices having four electrical terminals and the four terminals are connected to four isolated electrically conductive regions in certain of the pads of the second subset of pads.

12. The device structure of claim 7 wherein the other devices are selected from the group of active devices consisting of switches, sensors, accelerometers, regulators, interlocks, diodes, transistors, integrated circuits, MEMS devices, mechanical components, and warpage compensation circuits.

13. A ball grid array comprising:
a two-dimensional array of pads formed on a first major surface of a substrate, first and second subsets of the pads being connected to conductors that extend across or into the substrate, each pad of the second subset of the pads having a plurality of isolated electrically conductive regions that are connected to different conductors;
solder balls or solder bumps formed on the first subset of the pads, said solder balls or solder bumps having a first height; and
other devices formed on the second subset of the pads that have a height that is no more than the first height, wherein each of the other devices is directly mounted on one of the second subset of the pads, wherein each of the other devices comprises multiple terminals, and wherein each of the multiple terminals of one of the other devices is electrically connected to a different one of the plurality of isolated electrically conductive regions of one of the second subset of the pads.

14. The ball grid array of claim 13 wherein the other devices include devices having two electrical terminals and the two terminals are connected to two isolated electrically conductive regions in certain of the pads of the second subset of pads.

15. The ball grid array of claim 13 wherein the other devices are selected from the group consisting of resistors, capacitors and inductors.

16. The ball grid array of claim 13 wherein the other devices include devices having three electrical terminals and the three terminals are connected to three isolated electrically conductive regions in certain of the pads of the second subset of pads.

17. The ball grid array of claim 13 wherein the other devices include devices having four electrical terminals and the four terminals are connected to four isolated electrically conductive regions in certain of the pads of the second subset of pads.

18. The ball grid array of claim 13 wherein the other devices are selected from the group of active devices consisting of switches, sensors, accelerometers, regulators, interlocks, diodes, transistors, integrated circuits, MEMS devices, mechanical components, and warpage compensation circuits.

19. A method for forming a ball grid array comprising:
forming an array of bonding pads on a first major surface of a first substrate, a first group of the bonding pads each having a continuous electrically conductive surface and a second group of the bonding pads each having multiple electrically conductive elements separated from one another, wherein the first and second groups of the bonding pads are connected to conductors that extend across or into the first substrate;
mounting multi-terminal components directly on the bonding pads of the second group of bonding pads, wherein each

Assignees

• Altera Corp

Inventors

• Xie Yuanlin

Classifications

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07254

  changes in dispositions · CPC title