Packaging substrate having a through-holed interposer

Patent metadata

Field	Value
Publication number	US-9460992-B2
Application number	US-201514641901-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Jul 26, 2012
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

First claim

What is claimed is:

1. A packaging substrate, comprising:
an interposer having opposing first and second surfaces and a plurality of conductive gels interconnecting the first surface and the second surface, wherein each of the conductive gels has opposing first and second ends, such that the first end protrudes from the first surface of the interposer, and a circuit redistribution structure is disposed on the second surface of the interposer and electrically connected to the second ends of the conductive gels;
an encapsulating layer that encapsulates and is in direct contact with side surfaces and the first surface of the interposer; and
a circuit built-up structure disposed on the encapsulating layer above the first surface of the interposer and electrically connected to the first ends of the conductive gels.

2. The packaging substrate of claim 1 , wherein the circuit built-up structure has at least a built-up dielectric layer, and a built-up circuit layer formed on the built-up dielectric layer and electrically connected to the first ends of the conductive gels.

3. The packaging substrate of claim 2 , wherein the built-up circuit layer is embedded in the encapsulating layer.

4. The packaging substrate of claim 3 , wherein the circuit built-up structure further comprises a plurality of built-up conductive vias formed in the built-up dielectric layer and electrically connected to the built-up circuit layer.

5. The packaging substrate of claim 1 , wherein the circuit redistribution structure has at least a redistribution dielectric layer, and a redistribution circuit layer formed on the redistribution dielectric layer and electrically connected to the second ends of the conductive gels.

6. The packaging substrate of claim 5 , wherein the circuit redistribution structure further has a plurality of redistribution conductive vias formed in the redistribution dielectric layer and electrically connected to the redistribution circuit layer.

Assignees

• Unimicron Technology Corp
• Unimicron Technology Corp

Inventors

• Tseng Tzyy-Jang
• Hu Dyi-Chung
• Chan Ying-Chih

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title