Semiconductor module

US9460981B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9460981-B2
Application numberUS-201514937383-A
CountryUS
Kind codeB2
Filing dateNov 10, 2015
Priority dateOct 29, 2013
Publication dateOct 4, 2016
Grant dateOct 4, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor module uses pin bonding and improves cooling capacity. The semiconductor module includes a semiconductor element; a pin electrically and thermally connected to an upper surface of the semiconductor element; a pin wiring substrate having a first metal film and a second metal film respectively provided on the rear and front surfaces of a pin wiring insulating substrate, the first metal film being bonded to the pin; a first DCB substrate having a third metal film and a fourth metal film respectively provided on the rear and front surfaces of a first ceramic insulating substrate, the third metal film being bonded to a lower surface of the semiconductor element; a first cooler thermally connected to the fourth metal film; and a second cooler that thermally connected to the second metal film.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor module comprising: a semiconductor element; a pin electrically and thermally connected to an upper surface of the semiconductor element; a pin wiring substrate including a pin wiring insulating substrate, a first metal film provided on a rear surface of the pin wiring insulating substrate, and a second metal film provided on a front surface of the pin wiring insulating substrate, the first metal film being bonded to the pin; a first DCB substrate including a first ceramic insulating substrate, a third metal film provided on a front surface of the first ceramic insulating substrate, and a fourth metal film provided on a rear surface of the first ceramic insulating substrate, the third metal film being bonded to a lower surface of the semiconductor element; a first cooler thermally connected to the fourth metal film; and a second cooler thermally connected to the second metal film. 2. The semiconductor module according to claim 1 , wherein the pin wiring insulating substrate is made of a material selected from the group consisting of Si 3 N 4 , AlN and Al 2 O 3 . 3. The semiconductor module according to claim 1 , further comprising: a second DCB substrate including a second ceramic insulating substrate, a fifth metal film provided on a rear surface of the second ceramic insulating substrate, and a sixth metal film provided on a front surface of the second ceramic insulating substrate, wherein the second DCB substrate is provided between the second metal film and the second cooler so as to be thermally connected to the second metal film and the second cooler. 4. The semiconductor module according to claim 1 , further comprising a heat spreader provided between the second metal film and the second cooler so as to be thermally connected to the second metal film and the second cooler. 5. The semiconductor module according to claim 1 , wherein a plurality of sets of the semiconductor element and the pin is provided. 6. The semiconductor module according to claim 1 , wherein the semiconductor element includes an input terminal and an output terminal extending from between the first cooler and the second cooler to an outside. 7. A semiconductor module comprising: a plurality of semiconductor module units, each having, as a unit module, the semiconductor module according to claim 1 , wherein the plurality of semiconductor module units is arranged in a row such that side surfaces from which the input and output terminals of the semiconductor elements do not protrude face each other. 8. The semiconductor module according to claim 6 , wherein each of the first cooler and the second cooler is integrally provided so as to cover an entire row of the module units. 9. The semiconductor module according to claim 1 , wherein the semiconductor module is sealed with a sealing resin except for the first cooler, a surface which is thermally connected to the first cooler, the second cooler, and a surface which is thermally connected to the second cooler in the semiconductor module.

Assignees

Inventors

Classifications

  • on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

  • by flowing liquids, e.g. forced water cooling · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

  • Package configurations · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9460981B2 cover?
A semiconductor module uses pin bonding and improves cooling capacity. The semiconductor module includes a semiconductor element; a pin electrically and thermally connected to an upper surface of the semiconductor element; a pin wiring substrate having a first metal film and a second metal film respectively provided on the rear and front surfaces of a pin wiring insulating substrate, the first …
Who is the assignee on this patent?
Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W40/255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).