Method for fabricating semiconductor devices

Patent metadata

Field	Value
Publication number	US-9460935-B2
Application number	US-201514840835-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Oct 24, 2014
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

The invention relates to a method for fabricating a semiconductor device. The method comprises forming a first etching layer and a second etching layer stacked on a substrate, and forming a recess region by etching the first and second etching layers under plasma generated from an etching gas including a compound. The compound comprises at least one of 1,1,1,2,3,3-hexafluoropropane, 2,2,2-trifluoroethane-1-thiol, 1,1,1,3,3-pentafluoropropane, 1,1,2,2,3-pentafluoropropane and 1,1,2,2-tetrafluoro-1-iodoethane, 2,3,3,3-tetrafluoropropene and 1,1-difluoroethene.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a first etching layer and a second etching layer stacked on a substrate; and
forming a recess region by etching the first and second etching layers under plasma generated from an etching gas comprising a compound represented by Formula 1 or 2,

wherein the first etching layer comprises a material different from that of the second etching layer,
wherein R 1 is F or CF 3 , R 2 is CHF 2 , CH 2 F, I, SH or SOH, and R 3 and R 4 are independently selected from H, F or CHF 2 , and
wherein R 5 is F or CF 3 and R 6 is F, CHF 2 or CH 2 F.

2. The method of claim 1 , wherein the first and second etching layers are etched by a single process with plasma generated from the etching gas.

3. The method of claim 1 , wherein the first etching layer comprises a silicon oxide layer and the second etching layer comprises one of a silicon nitride layer and a silicon oxynitride layer.

4. The method of claim 1 , wherein the compound represented by Formula 1 comprises at least one of 1,1,1,2,3,3-hexafluoropropane, 2,2,2-trifluoroethane-1-thiol, 1,1,1,3,3-pentafluoropropane, 1,1,2,2,3-pentafluoropropane and 1,1,2,2-tetrafluoro-1-iodoethane, and
wherein the compound represented by Formula 2 comprises at least one of 2,3,3,3-tetrafluoropropene and 1,1-difluoroethene.

5. The method of claim 1 , wherein the plasma generated from the etching gas provides a first active species, a second active species and a third active species, wherein:
the first active species comprises at least one selected from the group consisting of CF 3 + , CF 2 + and CF + ;
the second active species comprises at least one selected from CHF 2 + or CH 2 F + ; and
the third reactive species comprises at least one selected from the group consisting of C x F y , S, SO and I.

6. The method of claim 5 , wherein the third active species comprises C x F y with a ratio of x to y (x:y) of 1 or more.

7. The method of claim 1 , wherein the etching gas further comprises at least one compound selected from the group consisting of C 4 F 8 , C 4 F 6 and O 2 .

8. The method of claim 1 , wherein the etching gas comprises least two compounds represented by Formula 1 or 2.

9. The method of claim 1 , wherein the etching is performed under a pressure of 1 mTorr to 200 mTorr at a temperature of 25° C. to 200° C.

10. The method of claim 1 , wherein the recess region has an aspect ratio of 5 to 150.

11. The method of claim 1 , wherein the recess region comprises a hole extending a direction perpendicular to a top surface of the substrate or a trench extending a direction parallel to the top surface of the substrate.

12. The method of claim 1 , wherein before forming the recess region, the method further comprises forming a mask pattern on the first and second etching layers, the mask pattern including an opening to define a plan shape of the recess region, and
wherein the etching gas selectively etches the first and second etching layers.

13. The method of claim 1 , wherein forming the first and second etching layers comprises stacking sacrificial layers and insulating layers alternately and repeatedly on the substrate to form a thin-film structure,
wherein the recess region comprises a channel hole penetrating the thin-film structure to expose the substrate.

14. The method of claim 1 , wherein forming the first and second etching layers comprises stacking sacrificial layers and insulating layers alternately and repeatedly on the substrate to form a thin-film structure,
wherein the recess region comprises a trench penetrating the thin-film structure to expose the substrate and extending in a direction parallel to a top surface of the substrate.

15. A method for fabricating a semiconductor device, the method comprising:
forming an etching layer on a substrate; and
forming a recess region by etching the etching layer under plasma generated from an etching gas including a compound represented by Formula 1,

wherein R 1 is F or CF 3 , R 2 is I, SH or SOH, R 3 and R 4 are independently selected from H, F or CHF 2 .

16. The method of claim 15 , wherein the etching layer comprises a first etching layer and a second etching layer sequentially stacked on the substrate, the first etching layer including a silicon oxide layer and the second etching layer including one of a silicon nitride layer and a silicon oxynitride layer.

17. The method of claim 15 , wherein the etching gas further comprises at least one compound selected from the group consisting of C 4 F 8 , C 4 F 6 and O 2 .

18. The method of claim 15 , wherein the etching gas further comprises O 2 , wherein O 2 is present at a mole fraction of O 2 ranging from 0.5 to 1.0 based on the compound represented by Formula 1.

19. The method of claim 15 , wherein the compound represented by Formula 1 comprises at least one of 2,2,2-trifluoroethane-1-thiol and 1,1,2,2-tetrafluoro-1-iodoethane.

20. A method for fabricating a semiconductor device, the method comprising:
providing a substrate comprising a device isolation pattern, wherein the device isolation pattern defines an active region;
forming a gate electrode in the substrate to cross the active region;
forming first and second impurity regions adjacent to both sides of the gate electrode, respectively, and in the active region;
forming a first insulating layer and a second insulating layer stacked on the active region, the second insulating layer comprising a material different from that of the first insulating layer; and
forming a contact hole by etching the first and second insulating layers in a single process with plasma generated from an etching gas comprising a compound represented by Formula 1 or 2,

wherein R 1 is F or CF 3 , R 2 is CHF 2 , CH 2 F, I, SH or SOH, and R 3 and R 4 are independently selected from H, F or CHF 2 , and
wherein R 5 is F or CF 3 and R 6 is F, CHF 2 or CH 2 F.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Wonwoong

Classifications

• C09K13/00

  Etching, surface-brightening or pickling compositions (for glass C03C15/00, {C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338}; for metallic material C23F, C23G1/00, C25F1/00; {for semi-conductors H10P52/40}) · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title