Method of forming a strained silicon layer

Patent metadata

Field	Value
Publication number	US-9460923-B2
Application number	US-201414220406-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Mar 20, 2013
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

First claim

What is claimed is:

1. A method comprising:
forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate;
implanting atoms to amorphize said silicon layer and a lower portion of the strained silicon germanium layer, without amorphizing a surface portion of said strained silicon germanium layer; and
annealing, to at least partially relax the strained silicon germanium layer and to re-crystallize said amorphized lower portion of the strained silicon germanium layer and said amorphized silicon layer, so that the silicon layer becomes a strained silicon layer.

2. The method of claim 1 , wherein the silicon layer is formed over an amorphous layer disposed on the substrate.

3. The method of claim 2 , wherein during said implantation step, atoms are implanted to a maximum depth falling within said amorphous layer or within said substrate.

4. The method of claim 1 , wherein the implantation of atoms during said implantation step is localized using a mask.

5. The method of claim 1 , wherein said strained silicon germanium layer has a thickness of between 20 and 200 nm.

6. The method of claim 5 , wherein the strained silicon germanium layer has a thickness lower than the critical thickness below which SiGe grows, without defect, with the lattice parameter of the underlying silicon layer.

7. The method of claim 1 , wherein said strained silicon germanium layer has a germanium concentration of between 10 and 50 percent.

8. The method of claim 1 , wherein said surface portion has a thickness of at least 1 nm.

9. The method of claim 1 , wherein said annealing is performed at a temperature of between 500 and 1100° C.

10. The method of claim 1 , wherein said annealing comprises a first anneal of between 300 and 500° C. followed by a second anneal at a temperature greater than 500° C.

11. The method of claim 1 , wherein said annealing comprises laser or lamp annealing to superficially heat said strained silicon germanium layer.

12. The method of claim 1 , further comprising, after said annealing step, etching to at least partially remove said strained silicon germanium layer.

13. The method of claim 1 , further comprising the epitaxial growth of another layer on the strained silicon germanium layer.

14. A method comprising:
forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate;
without previously relaxing stress in the strained silicon germanium layer, implanting atoms to amorphize said silicon layer and a lower portion of the strained silicon germanium layer below a not amorphized surface portion of said strained silicon germanium layer; and
annealing to at least partially relax the strained silicon germanium layer and to re-crystallize said amorphized lower portion of the strained silicon germanium layer and said amorphized silicon layer to make the silicon layer into a strained silicon layer.

Assignees

• St Microelectronics Crolles 2 Sas
• Commissariat L Energie Atomique Et Aux Energies Alternatives
• Commisariat A L'Energie Atomique Et Aux Energies Alternatives

Inventors

• Halimaoui Aomar
• Hartmann Jean-Michel

Classifications

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title