Pixel circuit and display device

US9460660B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9460660-B2
Application numberUS-201214366089-A
CountryUS
Kind codeB2
Filing dateDec 6, 2012
Priority dateDec 21, 2011
Publication dateOct 4, 2016
Grant dateOct 4, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit includes: a light emitting element; an n-channel drive transistor T 1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T 2 which is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor T 3 which is interposed between the source and a drain of the drive transistor T 1 , has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T 2 ; and a capacitance element which is interposed between the gate and the source of the drive transistor T 1 , and holds the light emission control voltage.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display device in which a plurality of pixel circuits are arranged in a row direction and a column direction to constitute a pixel circuit array, the pixel circuit comprising: a light emitting element which emits light by a light emission current flowing from an anode electrode to a cathode electrode; a first transistor element of an n-channel insulated gate thin-film transistor that has a source electrode connected with the anode electrode of the light emitting element, a gate electrode connected with a pixel node, and controls the light emission current in accordance with a light emission control voltage between the gate electrode and the source electrode; a first switch circuit which is interposed between a data signal line and the pixel node and is controlled for conduction/non-conduction in accordance with a voltage level of a first control terminal connected with a scan signal line; a second switch circuit which is interposed between the source electrode and a drain electrode of the first transistor element and is controlled for conduction/non-conduction in accordance with a voltage level of a second control terminal connected with the scan signal line, and comes into a conduction state at the time of conduction of the first switch circuit in accordance with a voltage level of the scan signal line, to selectivity short-circuit between the source electrode and the drain electrode of the first transistor; and a capacitance element which is interposed between the gate electrode and the source electrode of the first transistor element, and holds the light emission control voltage, wherein the pixel circuits arranged on an identical column each have one end of the first switch circuit connected to the data signal line extending in the column direction along the identical column, and the pixel circuits arranged on an identical row each have the first control terminal of the first switch circuit and the second control terminal of the second switch circuit connected to the scan signal line extending in the row direction along the identical row, and the drain electrode of the first transistor element connected to a light emission voltage supply line extending in the row direction along the identical row, the display device comprising: a data signal line drive circuit which individually drives the data signal line provided in plural; a scan signal line drive circuit which individually drives the scan signal line provided in plural; a light emission voltage supply line drive circuit which individually drives the light emission voltage supply line provided in plural; a monitor circuit which has a dummy pixel circuit configured by removing at least the light emitting element from the pixel circuit, and detects a current flowing between the drain electrode and the source electrode of the first transistor element provided in the dummy pixel circuit, to perform simulation monitoring of a change in electric characteristic of the first transistor element in the pixel circuit; and a correction circuit which corrects a voltage level of the data signal line driven by the data signal line drive circuit based on a current amount detected by the monitor circuit or a value equivalent to the current amount. 2. A display device, in which a plurality of pixel circuits are arranged in a row direction and a column direction to constitute a pixel circuit array, the pixel circuit comprising at least: a light emitting element which emits light by a light emission current flowing from an anode electrode to a cathode electrode; a first transistor element of an n-channel insulated gate thin-film transistor that has a source electrode connected with the anode electrode of the light emitting element, a gate electrode connected with a pixel node, and controls the light emission current in accordance with a light emission control voltage between the gate electrode and the source electrode; a first switch circuit which is interposed between a data signal line and the pixel node and is controlled for conduction/non-conduction in accordance with a voltage level of a first control terminal connected with a scan signal line; and a capacitance element which is interposed between the gate electrode of the first transistor element and the source electrode or a drain electrode of the first transistor element, the pixel circuits arranged on an identical column each have one end of the first switch circuit connected to the data signal line extending in the column direction along the identical column, and the pixel circuits arranged on an identical row each have the first control terminal of the first switch circuit connected to the scan signal line extending in the row direction along the identical row, and the drain electrode of the first transistor element connected directly or via another circuit element to a light emission voltage supply line extending in the row direction along the identical row, the display device comprising: a data signal line drive circuit which individually drives the data signal line provided in plural; a scan signal line drive circuit which individually drives the scan signal line provided in plural; a light emission voltage supply line drive circuit which individually drives the light emission voltage supply line provided in plural; a monitor circuit which has a dummy pixel circuit configured by removing at least the light emitting element from the pixel circuit, and detects a current flowing between the drain electrode and the source electrode of the first transistor element provided in the dummy pixel circuit, to perform simulation monitoring of a change in electric characteristic of the first transistor element in the pixel circuit; and a correction circuit which corrects a voltage level of the data signal line driven by the data signal line drive circuit based on a current amount detected by the monitor circuit or a value equivalent to the current amount. 3. The display device according to claim 2 , wherein the monitor circuit includes at least one dummy pixel circuit of claim 2 , in which one end of the first switch circuit is connected to at least one data signal line, and the first control terminal of the first switch circuit in the dummy pixel circuit is connected to a dummy scan signal line. 4. The display device according to claim 3 , wherein the dummy scan signal line is driven every time each of the scan signal lines on a plurality of rows is sequentially driven by the scan signal line drive circuit in order to simultaneously bring the first switch circuits in the pixel circuits on an identical row into a conduction state. 5. The display device according to claim 3 , wherein the dummy pixel circuit is configured by removing at least the light emitting element from the pixel circuit and by including a third switch circuit which is interposed between a corresponding one of the data signal lines and the drain electrode of the first transistor element, the third switch circuit being controlled for conduction/non-conduction in accordance with a voltage level of a third control terminal connected with a monitor control signal line. 6. The display device according to claim 3 , wherein the monitor circuit includes the dummy pixel circuit, in which one end of the first switch circuit is connected to the data signal line, with respect to each of the data signal lines, and the first control terminal of the first switch circuit in each dummy pixel circuit is connected to the dummy scan signal line extending in the row direction. 7. The display device according to claim 2 , wherein the dummy pixel circuit is configured by removing at least the light emitting element and the first switch circuit from the pixel circuit, and the m

Assignees

Inventors

Classifications

  • comprising a resonant cavity structure, e.g. Bragg reflector pair · CPC title

  • Reflective anodes, e.g. ITO combined with thick metallic layers · CPC title

  • Electricity · mapped topic

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • Details of dummy pixels or dummy lines in flat panels · CPC title

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What does patent US9460660B2 cover?
A pixel circuit includes: a light emitting element; an n-channel drive transistor T 1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T 2 which is inte…
Who is the assignee on this patent?
Sharp Kk
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).