Display device and bonding test system

US9460646B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9460646-B2
Application numberUS-201313919419-A
CountryUS
Kind codeB2
Filing dateJun 17, 2013
Priority dateNov 1, 2012
Publication dateOct 4, 2016
Grant dateOct 4, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a display panel having a glass substrate, a first input pad formed on the glass substrate and a second input pad formed on the glass substrate, and a driver integrated circuit mounted on the glass substrate of the display panel using a chip-on-glass (COG) method. The driver integrated circuit includes first and second input bumps respectively coupled to the first and second input pads, and an internal ground line coupled to the first and second input bumps. The first input bump of the driver IC receives a test signal through the first input pad when a COG bonding test is performed, and receives a ground voltage when the display device operates.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device, comprising: a display panel including a glass substrate, a first input pad formed on the glass substrate, and a second input pad formed on the glass substrate; and a driver integrated circuit (IC) mounted on the glass substrate of the display panel using a chip-on-glass (COG) method, the driver integrated circuit including a first input bump coupled to the first input pad, a second input bump coupled to the second input pad, and an internal ground line coupled to the first and second input bumps, wherein, when a COG bonding test for the glass substrate and the driver IC is performed by a bonding test device, the first input bump of the driver IC is configured to receive a test signal from the bonding test device through the first input pad, and is configured to provide the test signal to the bonding test device through the internal ground line, the second input bump and the second input pad, and wherein, when the display device operates, the first input bump of the driver IC is configured to receive a ground voltage through the first input pad, and is configured to provide the ground voltage to the internal ground line. 2. The display device of claim 1 , wherein the bonding test device performs the COG bonding test by measuring a resistance of a path of the test signal including a first bonding resistance between the first input pad and the first input bump and a second bonding resistance between the second input pad and the second input bump. 3. The display device of claim 1 , wherein the second input bump of the driver IC is a ground input bump configured to receive the ground voltage through the second input pad and to provide the ground voltage to the internal ground line when the display device operates. 4. The display device of claim 1 , wherein the second input bump of the driver IC is a signal input bump configured to receive a data signal through the second input pad when the display device operates. 5. The display device of claim 4 , wherein the driver IC further includes a diode coupled between the internal ground line and the second input bump, and wherein the diode is configured to transfer the test signal from the internal ground line to the second input bump when the COG bonding test is performed, and is configured to prevent the data signal from being transferred from the second input bump to the internal ground line when the display device operates. 6. The display device of claim 1 , wherein at least one of the first input bump and the second input bump is located at a center portion of the driver IC. 7. The display device of claim 1 , wherein at least one of the first input bump and the second input bump is located at a side portion of the driver IC. 8. The display device of claim 1 , wherein the second input bump is located at a center portion of the driver IC, wherein the driver IC further includes a third input bump coupled to the internal ground line and located at a left side portion of the driver IC, and a fourth input bump coupled to the internal ground line and located at a right side portion of the driver IC, and wherein the bonding test device performs the COG bonding test for the glass substrate and the center portion of the driver IC using a first path including the first input bump, the internal ground line and the second input bump, performs the COG bonding test for the glass substrate and the left side portion of the driver IC using a second path including the first input bump, the internal ground line and the third input bump, and performs the COG bonding test for the glass substrate and the right side portion of the driver IC using a third path including the first input bump, the internal ground line and the fourth input bump. 9. The display device of claim 1 , wherein the display panel further includes a third input pad formed on the glass substrate, a first output pad formed on the glass substrate, a second output pad formed on the glass substrate, and a first connecting line coupling the first output pad to the second output pad, wherein the driver IC further includes a first output bump coupled to the internal ground line and the first output pad, a second output bump coupled to the second output pad, a third input bump coupled to the third input pad, and a second connecting line coupling the second output bump to the third input bump, and wherein the bonding test device performs the COG bonding test using a path including the first input pad, the first input bump, the internal ground line, the first output pad, the first connecting line, the second output pad, the second output bump, the second connecting line, the third input bump and the third input pad. 10. The display device of claim 9 , wherein the bonding test device performs the COG bonding test by measuring a resistance of the path including a first bonding resistance between the first input pad and the first input bump, a second bonding resistance between the first output pad and the first output bump, a third bonding resistance between the second output pad and the second output bump, and a fourth bonding resistance between the third input pad and the third input bump. 11. The display device of claim 1 , further comprising: a flexible printed circuit (FPC) mounted on the glass substrate using a film-on-glass (FOG) method, the FPC coupled to the bonding test device when the COG bonding test is performed. 12. The display device of claim 11 , wherein the display panel further includes first and second FPC pads formed on the glass substrate, and first and second connecting lines coupling the first and second input pads to the first and second FPC pads, respectively, wherein the FPC includes a first FPC bump coupled to the first FPC pad, a second FPC bump coupled to the second FPC pad, a first FPC line coupled to the first FPC bump, and a second FPC line coupled to the second FPC bump, and wherein the bonding test device performs the COG bonding test for the glass substrate and the driver IC and a FOG bonding test for the glass substrate and the FPC by applying the test signal to the first FPC line and by receiving the applied test signal through a path including the first FPC line, the first FPC bump, the first FPC pad, the first connecting line, the first input pad, the first input bump, the internal ground line, the second input bump, the second input pad, the second connecting line, the second FPC pad, the second FPC bump and the second FPC line. 13. The display device of claim 12 , wherein the bonding test device performs the COG bonding test and the FOG bonding test by measuring a resistance of the path including a first bonding resistance between the first FPC pad and the first FPC bump, a second bonding resistance between the first input pad and the first input bump, a third bonding resistance between the second input pad and the second input bump, and a fourth bonding resistance between the second FPC pad and the second FPC bump. 14. A display device, comprising: a display panel including a glass substrate, first and second input pads formed on the glass substrate, first and second output pads formed on the glass substrate, and a first connecting line coupling the first output pad to the second output pad; and a driver integrated circuit (IC) mounted on the glass substrate of the display panel using a chip-on-glass (COG) method, the driver integrated circuit including first and second input bumps respectively coupled to the first and second input pads, first and second output bumps respectively coupled to the first and second output pads, an internal ground line co

Assignees

Inventors

Classifications

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • Conductors connecting electrodes to cell terminals · CPC title

  • G09F9/00Primary

    Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements (in which the variable information is permanently attached to a movable support G09F11/00; abacus G06C1/00; slide-rules G06G1/00) · CPC title

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What does patent US9460646B2 cover?
A display device includes a display panel having a glass substrate, a first input pad formed on the glass substrate and a second input pad formed on the glass substrate, and a driver integrated circuit mounted on the glass substrate of the display panel using a chip-on-glass (COG) method. The driver integrated circuit includes first and second input bumps respectively coupled to the first and s…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).